3028-dts-ls1043-update-dts-for-ls1043.patch 13 KB

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  1. From ad6176d72132d020317db1496be1485056ac88d7 Mon Sep 17 00:00:00 2001
  2. From: Liu Gang <Gang.Liu@nxp.com>
  3. Date: Mon, 6 Jun 2016 15:46:00 +0800
  4. Subject: [PATCH 28/70] dts/ls1043: update dts for ls1043
  5. Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
  6. ---
  7. arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 59 +++++
  8. arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 264 +++++++++++++++++++-
  9. .../boot/dts/freescale/qoriq-qman1-portals.dtsi | 10 +-
  10. 3 files changed, 321 insertions(+), 12 deletions(-)
  11. --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
  12. +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
  13. @@ -50,6 +50,10 @@
  14. / {
  15. model = "LS1043A RDB Board";
  16. compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
  17. +
  18. + aliases {
  19. + crypto = &crypto;
  20. + };
  21. };
  22. &i2c0 {
  23. @@ -108,6 +112,35 @@
  24. };
  25. };
  26. +&dspi0 {
  27. + bus-num = <0>;
  28. + status = "okay";
  29. +
  30. + flash@0 {
  31. + #address-cells = <1>;
  32. + #size-cells = <1>;
  33. + compatible = "n25q128a13", "jedec,spi-nor"; /* 16MB */
  34. + reg = <0>;
  35. + spi-max-frequency = <1000000>; /* input clock */
  36. + };
  37. +
  38. + slic@2 {
  39. + compatible = "maxim,ds26522";
  40. + reg = <2>;
  41. + spi-max-frequency = <2000000>;
  42. + fsl,spi-cs-sck-delay = <100>;
  43. + fsl,spi-sck-cs-delay = <50>;
  44. + };
  45. +
  46. + slic@3 {
  47. + compatible = "maxim,ds26522";
  48. + reg = <3>;
  49. + spi-max-frequency = <2000000>;
  50. + fsl,spi-cs-sck-delay = <100>;
  51. + fsl,spi-sck-cs-delay = <50>;
  52. + };
  53. +};
  54. +
  55. &duart0 {
  56. status = "okay";
  57. };
  58. @@ -176,7 +209,33 @@
  59. mdio@fd000 {
  60. aqr105_phy: ethernet-phy@c {
  61. compatible = "ethernet-phy-ieee802.3-c45";
  62. + interrupts = <0 132 4>;
  63. reg = <0x1>;
  64. };
  65. };
  66. };
  67. +
  68. +&uqe {
  69. + ucc_hdlc: ucc@2000 {
  70. + compatible = "fsl,ucc_hdlc";
  71. + rx-clock-name = "clk8";
  72. + tx-clock-name = "clk9";
  73. + fsl,rx-sync-clock = "rsync_pin";
  74. + fsl,tx-sync-clock = "tsync_pin";
  75. + fsl,tx-timeslot = <0xfffffffe>;
  76. + fsl,rx-timeslot = <0xfffffffe>;
  77. + fsl,tdm-framer-type = "e1";
  78. + fsl,tdm-mode = "normal";
  79. + fsl,tdm-id = <0>;
  80. + fsl,siram-entry-id = <0>;
  81. + fsl,tdm-interface;
  82. + };
  83. +
  84. + ucc_serial: ucc@2200 {
  85. + device_type = "serial";
  86. + compatible = "ucc_uart";
  87. + port-number = <0>;
  88. + rx-clock-name = "brg2";
  89. + tx-clock-name = "brg2";
  90. + };
  91. +};
  92. --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
  93. +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
  94. @@ -44,6 +44,8 @@
  95. * OTHER DEALINGS IN THE SOFTWARE.
  96. */
  97. +#include <dt-bindings/thermal/thermal.h>
  98. +
  99. / {
  100. compatible = "fsl,ls1043a";
  101. interrupt-parent = <&gic>;
  102. @@ -75,6 +77,7 @@
  103. compatible = "arm,cortex-a53";
  104. reg = <0x0>;
  105. clocks = <&clockgen 1 0>;
  106. + #cooling-cells = <2>;
  107. };
  108. cpu1: cpu@1 {
  109. @@ -118,6 +121,8 @@
  110. <1 14 0x1>, /* Physical Non-Secure PPI */
  111. <1 11 0x1>, /* Virtual PPI */
  112. <1 10 0x1>; /* Hypervisor PPI */
  113. + arm,reread-timer;
  114. + fsl,erratum-a008585;
  115. };
  116. pmu {
  117. @@ -162,11 +167,64 @@
  118. big-endian;
  119. };
  120. + crypto: crypto@1700000 {
  121. + compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
  122. + "fsl,sec-v4.0";
  123. + fsl,sec-era = <3>;
  124. + #address-cells = <1>;
  125. + #size-cells = <1>;
  126. + ranges = <0x0 0x00 0x1700000 0x100000>;
  127. + reg = <0x00 0x1700000 0x0 0x100000>;
  128. + interrupts = <0 75 0x4>;
  129. +
  130. + sec_jr0: jr@10000 {
  131. + compatible = "fsl,sec-v5.4-job-ring",
  132. + "fsl,sec-v5.0-job-ring",
  133. + "fsl,sec-v4.0-job-ring";
  134. + reg = <0x10000 0x10000>;
  135. + interrupts = <0 71 0x4>;
  136. + };
  137. +
  138. + sec_jr1: jr@20000 {
  139. + compatible = "fsl,sec-v5.4-job-ring",
  140. + "fsl,sec-v5.0-job-ring",
  141. + "fsl,sec-v4.0-job-ring";
  142. + reg = <0x20000 0x10000>;
  143. + interrupts = <0 72 0x4>;
  144. + };
  145. +
  146. + sec_jr2: jr@30000 {
  147. + compatible = "fsl,sec-v5.4-job-ring",
  148. + "fsl,sec-v5.0-job-ring",
  149. + "fsl,sec-v4.0-job-ring";
  150. + interrupts = <0 73 0x4>;
  151. + };
  152. +
  153. + sec_jr3: jr@40000 {
  154. + compatible = "fsl,sec-v5.4-job-ring",
  155. + "fsl,sec-v5.0-job-ring",
  156. + "fsl,sec-v4.0-job-ring";
  157. + reg = <0x40000 0x10000>;
  158. + interrupts = <0 74 0x4>;
  159. + };
  160. + };
  161. +
  162. dcfg: dcfg@1ee0000 {
  163. compatible = "fsl,ls1043a-dcfg", "syscon";
  164. reg = <0x0 0x1ee0000 0x0 0x10000>;
  165. };
  166. + reset: reset@1EE00B0 {
  167. + compatible = "fsl,ls-reset";
  168. + reg = <0x0 0x1EE00B0 0x0 0x4>;
  169. + big-endian;
  170. + };
  171. +
  172. + rcpm: rcpm@1ee2000 {
  173. + compatible = "fsl,ls1043a-rcpm", "fsl,qoriq-rcpm-2.1";
  174. + reg = <0x0 0x1ee2000 0x0 0x10000>;
  175. + };
  176. +
  177. ifc: ifc@1530000 {
  178. compatible = "fsl,ifc", "simple-bus";
  179. reg = <0x0 0x1530000 0x0 0x10000>;
  180. @@ -501,6 +559,82 @@
  181. };
  182. };
  183. + tmu: tmu@1f00000 {
  184. + compatible = "fsl,qoriq-tmu", "fsl,ls1043a-tmu";
  185. + reg = <0x0 0x1f00000 0x0 0x10000>;
  186. + interrupts = <0 33 0x4>;
  187. + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
  188. + fsl,tmu-calibration = <0x00000000 0x00000026
  189. + 0x00000001 0x0000002d
  190. + 0x00000002 0x00000032
  191. + 0x00000003 0x00000039
  192. + 0x00000004 0x0000003f
  193. + 0x00000005 0x00000046
  194. + 0x00000006 0x0000004d
  195. + 0x00000007 0x00000054
  196. + 0x00000008 0x0000005a
  197. + 0x00000009 0x00000061
  198. + 0x0000000a 0x0000006a
  199. + 0x0000000b 0x00000071
  200. +
  201. + 0x00010000 0x00000025
  202. + 0x00010001 0x0000002c
  203. + 0x00010002 0x00000035
  204. + 0x00010003 0x0000003d
  205. + 0x00010004 0x00000045
  206. + 0x00010005 0x0000004e
  207. + 0x00010006 0x00000057
  208. + 0x00010007 0x00000061
  209. + 0x00010008 0x0000006b
  210. + 0x00010009 0x00000076
  211. +
  212. + 0x00020000 0x00000029
  213. + 0x00020001 0x00000033
  214. + 0x00020002 0x0000003d
  215. + 0x00020003 0x00000049
  216. + 0x00020004 0x00000056
  217. + 0x00020005 0x00000061
  218. + 0x00020006 0x0000006d
  219. +
  220. + 0x00030000 0x00000021
  221. + 0x00030001 0x0000002a
  222. + 0x00030002 0x0000003c
  223. + 0x00030003 0x0000004e>;
  224. + big-endian;
  225. + #thermal-sensor-cells = <1>;
  226. + };
  227. +
  228. + thermal-zones {
  229. + cpu_thermal: cpu-thermal {
  230. + polling-delay-passive = <1000>;
  231. + polling-delay = <5000>;
  232. +
  233. + thermal-sensors = <&tmu 3>;
  234. +
  235. + trips {
  236. + cpu_alert: cpu-alert {
  237. + temperature = <85000>;
  238. + hysteresis = <2000>;
  239. + type = "passive";
  240. + };
  241. + cpu_crit: cpu-crit {
  242. + temperature = <95000>;
  243. + hysteresis = <2000>;
  244. + type = "critical";
  245. + };
  246. + };
  247. +
  248. + cooling-maps {
  249. + map0 {
  250. + trip = <&cpu_alert>;
  251. + cooling-device =
  252. + <&cpu0 THERMAL_NO_LIMIT
  253. + THERMAL_NO_LIMIT>;
  254. + };
  255. + };
  256. + };
  257. + };
  258. +
  259. dspi0: dspi@2100000 {
  260. compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
  261. #address-cells = <1>;
  262. @@ -527,6 +661,20 @@
  263. status = "disabled";
  264. };
  265. + qspi: quadspi@1550000 {
  266. + compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
  267. + #address-cells = <1>;
  268. + #size-cells = <0>;
  269. + reg = <0x0 0x1550000 0x0 0x10000>,
  270. + <0x0 0x40000000 0x0 0x4000000>;
  271. + reg-names = "QuadSPI", "QuadSPI-memory";
  272. + interrupts = <0 99 0x4>;
  273. + clock-names = "qspi_en", "qspi";
  274. + clocks = <&clockgen 4 0>, <&clockgen 4 0>;
  275. + big-endian;
  276. + status = "disabled";
  277. + };
  278. +
  279. i2c0: i2c@2180000 {
  280. compatible = "fsl,vf610-i2c";
  281. #address-cells = <1>;
  282. @@ -602,8 +750,8 @@
  283. clocks = <&clockgen 4 0>;
  284. };
  285. - gpio1: gpio@2300000 {
  286. - compatible = "fsl,ls1043a-gpio";
  287. + gpio0: gpio@2300000 {
  288. + compatible = "fsl,qoriq-gpio";
  289. reg = <0x0 0x2300000 0x0 0x10000>;
  290. interrupts = <0 66 0x4>;
  291. gpio-controller;
  292. @@ -612,8 +760,8 @@
  293. #interrupt-cells = <2>;
  294. };
  295. - gpio2: gpio@2310000 {
  296. - compatible = "fsl,ls1043a-gpio";
  297. + gpio1: gpio@2310000 {
  298. + compatible = "fsl,qoriq-gpio";
  299. reg = <0x0 0x2310000 0x0 0x10000>;
  300. interrupts = <0 67 0x4>;
  301. gpio-controller;
  302. @@ -622,8 +770,8 @@
  303. #interrupt-cells = <2>;
  304. };
  305. - gpio3: gpio@2320000 {
  306. - compatible = "fsl,ls1043a-gpio";
  307. + gpio2: gpio@2320000 {
  308. + compatible = "fsl,qoriq-gpio";
  309. reg = <0x0 0x2320000 0x0 0x10000>;
  310. interrupts = <0 68 0x4>;
  311. gpio-controller;
  312. @@ -632,8 +780,8 @@
  313. #interrupt-cells = <2>;
  314. };
  315. - gpio4: gpio@2330000 {
  316. - compatible = "fsl,ls1043a-gpio";
  317. + gpio3: gpio@2330000 {
  318. + compatible = "fsl,qoriq-gpio";
  319. reg = <0x0 0x2330000 0x0 0x10000>;
  320. interrupts = <0 134 0x4>;
  321. gpio-controller;
  322. @@ -642,6 +790,70 @@
  323. #interrupt-cells = <2>;
  324. };
  325. + uqe: uqe@2400000 {
  326. + #address-cells = <1>;
  327. + #size-cells = <1>;
  328. + device_type = "qe";
  329. + compatible = "fsl,qe", "simple-bus";
  330. + ranges = <0x0 0x0 0x2400000 0x40000>;
  331. + reg = <0x0 0x2400000 0x0 0x480>;
  332. + brg-frequency = <100000000>;
  333. + bus-frequency = <200000000>;
  334. +
  335. + fsl,qe-num-riscs = <1>;
  336. + fsl,qe-num-snums = <28>;
  337. +
  338. + qeic: qeic@80 {
  339. + compatible = "fsl,qe-ic";
  340. + reg = <0x80 0x80>;
  341. + #address-cells = <0>;
  342. + interrupt-controller;
  343. + #interrupt-cells = <1>;
  344. + interrupts = <0 77 0x04 0 77 0x04>;
  345. + };
  346. +
  347. + si1: si@700 {
  348. + #address-cells = <1>;
  349. + #size-cells = <0>;
  350. + compatible = "fsl,qe-si";
  351. + reg = <0x700 0x80>;
  352. + };
  353. +
  354. + siram1: siram@1000 {
  355. + #address-cells = <1>;
  356. + #size-cells = <1>;
  357. + compatible = "fsl,qe-siram";
  358. + reg = <0x1000 0x800>;
  359. + };
  360. +
  361. + ucc@2000 {
  362. + cell-index = <1>;
  363. + reg = <0x2000 0x200>;
  364. + interrupts = <32>;
  365. + interrupt-parent = <&qeic>;
  366. + };
  367. +
  368. + ucc@2200 {
  369. + cell-index = <3>;
  370. + reg = <0x2200 0x200>;
  371. + interrupts = <34>;
  372. + interrupt-parent = <&qeic>;
  373. + };
  374. +
  375. + muram@10000 {
  376. + #address-cells = <1>;
  377. + #size-cells = <1>;
  378. + compatible = "fsl,qe-muram", "fsl,cpm-muram";
  379. + ranges = <0x0 0x10000 0x6000>;
  380. +
  381. + data-only@0 {
  382. + compatible = "fsl,qe-muram-data",
  383. + "fsl,cpm-muram-data";
  384. + reg = <0x0 0x6000>;
  385. + };
  386. + };
  387. + };
  388. +
  389. lpuart0: serial@2950000 {
  390. compatible = "fsl,ls1021a-lpuart";
  391. reg = <0x0 0x2950000 0x0 0x1000>;
  392. @@ -696,6 +908,15 @@
  393. status = "disabled";
  394. };
  395. + ftm0: ftm0@29d0000 {
  396. + compatible = "fsl,ftm-alarm";
  397. + reg = <0x0 0x29d0000 0x0 0x10000>;
  398. + interrupts = <0 86 0x4>;
  399. + big-endian;
  400. + rcpm-wakeup = <&rcpm 0x0 0x20000000>;
  401. + status = "okay";
  402. + };
  403. +
  404. wdog0: wdog@2ad0000 {
  405. compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
  406. reg = <0x0 0x2ad0000 0x0 0x10000>;
  407. @@ -726,6 +947,8 @@
  408. reg = <0x0 0x2f00000 0x0 0x10000>;
  409. interrupts = <0 60 0x4>;
  410. dr_mode = "host";
  411. + configure-gfladj;
  412. + snps,dis_rxdet_inp3_quirk;
  413. };
  414. usb1: usb3@3000000 {
  415. @@ -733,6 +956,8 @@
  416. reg = <0x0 0x3000000 0x0 0x10000>;
  417. interrupts = <0 61 0x4>;
  418. dr_mode = "host";
  419. + configure-gfladj;
  420. + snps,dis_rxdet_inp3_quirk;
  421. };
  422. usb2: usb3@3100000 {
  423. @@ -740,6 +965,8 @@
  424. reg = <0x0 0x3100000 0x0 0x10000>;
  425. interrupts = <0 63 0x4>;
  426. dr_mode = "host";
  427. + configure-gfladj;
  428. + snps,dis_rxdet_inp3_quirk;
  429. };
  430. sata: sata@3200000 {
  431. @@ -749,6 +976,20 @@
  432. clocks = <&clockgen 4 0>;
  433. };
  434. + qdma: qdma@8380000 {
  435. + compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
  436. + reg = <0x0 0x838f000 0x0 0x11000 /* Controller regs */
  437. + 0x0 0x83a0000 0x0 0x40000>; /* Block regs */
  438. + interrupts = <0 152 0x4>,
  439. + <0 39 0x4>;
  440. + interrupt-names = "qdma-error", "qdma-queue";
  441. + channels = <8>;
  442. + queues = <2>;
  443. + status-sizes = <64>;
  444. + queue-sizes = <64 64>;
  445. + big-endian;
  446. + };
  447. +
  448. msi1: msi-controller1@1571000 {
  449. compatible = "fsl,1s1043a-msi";
  450. reg = <0x0 0x1571000 0x0 0x4>,
  451. @@ -787,6 +1028,7 @@
  452. #address-cells = <3>;
  453. #size-cells = <2>;
  454. device_type = "pci";
  455. + dma-coherent;
  456. num-lanes = <4>;
  457. bus-range = <0x0 0xff>;
  458. ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
  459. @@ -811,6 +1053,7 @@
  460. #address-cells = <3>;
  461. #size-cells = <2>;
  462. device_type = "pci";
  463. + dma-coherent;
  464. num-lanes = <2>;
  465. bus-range = <0x0 0xff>;
  466. ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
  467. @@ -835,6 +1078,7 @@
  468. #address-cells = <3>;
  469. #size-cells = <2>;
  470. device_type = "pci";
  471. + dma-coherent;
  472. num-lanes = <2>;
  473. bus-range = <0x0 0xff>;
  474. ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
  475. @@ -897,8 +1141,8 @@
  476. alignment = <0 0x1000000>;
  477. };
  478. qman_fqd: qman-fqd {
  479. - size = <0 0x400000>;
  480. - alignment = <0 0x400000>;
  481. + size = <0 0x800000>;
  482. + alignment = <0 0x800000>;
  483. };
  484. qman_pfdr: qman-pfdr {
  485. size = <0 0x2000000>;
  486. --- a/arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi
  487. +++ b/arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi
  488. @@ -132,5 +132,11 @@
  489. compatible = "fsl,cgrid-range";
  490. fsl,cgrid-range = <0 256>;
  491. };
  492. -
  493. -};
  494. \ No newline at end of file
  495. + qman-ceetm@0 {
  496. + compatible = "fsl,qman-ceetm";
  497. + fsl,ceetm-lfqid-range = <0xf00000 0x1000>;
  498. + fsl,ceetm-sp-range = <0 12>;
  499. + fsl,ceetm-lni-range = <0 8>;
  500. + fsl,ceetm-channel-range = <0 32>;
  501. + };
  502. +};