653-0005-rtl8xxxu-First-stab-at-rtl8188e_power_on.patch 2.6 KB

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  1. From a7c3d46915bce6d84e61e684e76564b034bdc1a9 Mon Sep 17 00:00:00 2001
  2. From: Jes Sorensen <Jes.Sorensen@redhat.com>
  3. Date: Mon, 27 Jun 2016 17:08:30 -0400
  4. Subject: [PATCH] rtl8xxxu: First stab at rtl8188e_power_on()
  5. Code based on code from Andrea Merello.
  6. Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com>
  7. ---
  8. .../net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c | 82 ++++++++++++++++++++++
  9. 1 file changed, 82 insertions(+)
  10. --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c
  11. +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c
  12. @@ -92,8 +92,90 @@ static int rtl8188eu_load_firmware(struc
  13. return ret;
  14. }
  15. +static int rtl8188e_emu_to_active(struct rtl8xxxu_priv *priv)
  16. +{
  17. + u8 val8;
  18. + u32 val32;
  19. + u16 val16;
  20. + int count, ret = 0;
  21. +
  22. + /* wait till 0x04[17] = 1 power ready*/
  23. + for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
  24. + val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
  25. + if (val32 & BIT(17))
  26. + break;
  27. +
  28. + udelay(10);
  29. + }
  30. +
  31. + if (!count) {
  32. + ret = -EBUSY;
  33. + goto exit;
  34. + }
  35. +
  36. + /* reset baseband */
  37. + val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
  38. + val8 &= ~(SYS_FUNC_BBRSTB | SYS_FUNC_BB_GLB_RSTN);
  39. + rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
  40. +
  41. + /*0x24[23] = 2b'01 schmit trigger */
  42. + val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
  43. + val32 |= BIT(23);
  44. + rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
  45. +
  46. + /* 0x04[15] = 0 disable HWPDN (control by DRV)*/
  47. + val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
  48. + val16 &= ~APS_FSMCO_HW_POWERDOWN;
  49. + rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
  50. +
  51. + /*0x04[12:11] = 2b'00 disable WL suspend*/
  52. + val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
  53. + val16 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE);
  54. + rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
  55. +
  56. + /* set, then poll until 0 */
  57. + val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
  58. + val32 |= APS_FSMCO_MAC_ENABLE;
  59. + rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
  60. +
  61. + for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
  62. + val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
  63. + if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
  64. + ret = 0;
  65. + break;
  66. + }
  67. + udelay(10);
  68. + }
  69. +
  70. + if (!count) {
  71. + ret = -EBUSY;
  72. + goto exit;
  73. + }
  74. +
  75. + /* LDO normal mode*/
  76. + val8 = rtl8xxxu_read8(priv, REG_LPLDO_CTRL);
  77. + val8 &= ~BIT(4);
  78. + rtl8xxxu_write8(priv, REG_LPLDO_CTRL, val8);
  79. +
  80. +exit:
  81. + return ret;
  82. +}
  83. +
  84. +static int rtl8188eu_power_on(struct rtl8xxxu_priv *priv)
  85. +{
  86. + int ret;
  87. +
  88. + ret = rtl8188e_emu_to_active(priv);
  89. + if (ret)
  90. + goto exit;
  91. +
  92. +exit:
  93. + return ret;
  94. +}
  95. +
  96. struct rtl8xxxu_fileops rtl8188eu_fops = {
  97. .parse_efuse = rtl8188eu_parse_efuse,
  98. .load_firmware = rtl8188eu_load_firmware,
  99. + .power_on = rtl8188eu_power_on,
  100. .reset_8051 = rtl8xxxu_reset_8051,
  101. };