0040-Add-SMI-driver.patch 61 KB

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  1. From 75b517005b8a733b84735cacfa9cdb3f301db6a0 Mon Sep 17 00:00:00 2001
  2. From: Luke Wren <wren6991@gmail.com>
  3. Date: Sat, 5 Sep 2015 01:14:45 +0100
  4. Subject: [PATCH] Add SMI driver
  5. Signed-off-by: Luke Wren <wren6991@gmail.com>
  6. ---
  7. .../bindings/misc/brcm,bcm2835-smi-dev.txt | 17 +
  8. .../devicetree/bindings/misc/brcm,bcm2835-smi.txt | 48 +
  9. drivers/char/broadcom/Kconfig | 8 +
  10. drivers/char/broadcom/Makefile | 2 +-
  11. drivers/char/broadcom/bcm2835_smi_dev.c | 402 +++++++++
  12. drivers/misc/Kconfig | 8 +
  13. drivers/misc/Makefile | 1 +
  14. drivers/misc/bcm2835_smi.c | 985 +++++++++++++++++++++
  15. include/linux/broadcom/bcm2835_smi.h | 391 ++++++++
  16. 9 files changed, 1861 insertions(+), 1 deletion(-)
  17. create mode 100644 Documentation/devicetree/bindings/misc/brcm,bcm2835-smi-dev.txt
  18. create mode 100644 Documentation/devicetree/bindings/misc/brcm,bcm2835-smi.txt
  19. create mode 100644 drivers/char/broadcom/bcm2835_smi_dev.c
  20. create mode 100644 drivers/misc/bcm2835_smi.c
  21. create mode 100644 include/linux/broadcom/bcm2835_smi.h
  22. --- /dev/null
  23. +++ b/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi-dev.txt
  24. @@ -0,0 +1,17 @@
  25. +* Broadcom BCM2835 SMI character device driver.
  26. +
  27. +SMI or secondary memory interface is a peripheral specific to certain Broadcom
  28. +SOCs, and is helpful for talking to things like parallel-interface displays
  29. +and NAND flashes (in fact, most things with a parallel register interface).
  30. +
  31. +This driver adds a character device which provides a user-space interface to
  32. +an instance of the SMI driver.
  33. +
  34. +Required properties:
  35. +- compatible: "brcm,bcm2835-smi-dev"
  36. +- smi_handle: a phandle to the smi node.
  37. +
  38. +Optional properties:
  39. +- None.
  40. +
  41. +
  42. --- /dev/null
  43. +++ b/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi.txt
  44. @@ -0,0 +1,48 @@
  45. +* Broadcom BCM2835 SMI driver.
  46. +
  47. +SMI or secondary memory interface is a peripheral specific to certain Broadcom
  48. +SOCs, and is helpful for talking to things like parallel-interface displays
  49. +and NAND flashes (in fact, most things with a parallel register interface).
  50. +
  51. +Required properties:
  52. +- compatible: "brcm,bcm2835-smi"
  53. +- reg: Should contain location and length of SMI registers and SMI clkman regs
  54. +- interrupts: *the* SMI interrupt.
  55. +- pinctrl-names: should be "default".
  56. +- pinctrl-0: the phandle of the gpio pin node.
  57. +- brcm,smi-clock-source: the clock source for clkman
  58. +- brcm,smi-clock-divisor: the integer clock divisor for clkman
  59. +- dmas: the dma controller phandle and the DREQ number (4 on a 2835)
  60. +- dma-names: the name used by the driver to request its channel.
  61. + Should be "rx-tx".
  62. +
  63. +Optional properties:
  64. +- None.
  65. +
  66. +Examples:
  67. +
  68. +8 data pin configuration:
  69. +
  70. +smi: smi@7e600000 {
  71. + compatible = "brcm,bcm2835-smi";
  72. + reg = <0x7e600000 0x44>, <0x7e1010b0 0x8>;
  73. + interrupts = <2 16>;
  74. + pinctrl-names = "default";
  75. + pinctrl-0 = <&smi_pins>;
  76. + brcm,smi-clock-source = <6>;
  77. + brcm,smi-clock-divisor = <4>;
  78. + dmas = <&dma 4>;
  79. + dma-names = "rx-tx";
  80. +
  81. + status = "okay";
  82. +};
  83. +
  84. +smi_pins: smi_pins {
  85. + brcm,pins = <2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
  86. + /* Alt 1: SMI */
  87. + brcm,function = <5 5 5 5 5 5 5 5 5 5 5 5 5 5>;
  88. + /* /CS, /WE and /OE are pulled high, as they are
  89. + generally active low signals */
  90. + brcm,pull = <2 2 2 2 2 2 0 0 0 0 0 0 0 0>;
  91. +};
  92. +
  93. --- a/drivers/char/broadcom/Kconfig
  94. +++ b/drivers/char/broadcom/Kconfig
  95. @@ -41,3 +41,11 @@ config BCM2835_DEVGPIOMEM
  96. on the 2835. Calling mmap(/dev/gpiomem) will map the GPIO
  97. register page to the user's pointer.
  98. +config BCM2835_SMI_DEV
  99. + tristate "Character device driver for BCM2835 Secondary Memory Interface"
  100. + depends on (MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835) && BCM2835_SMI
  101. + default m
  102. + help
  103. + This driver provides a character device interface (ioctl + read/write) to
  104. + Broadcom's Secondary Memory interface. The low-level functionality is provided
  105. + by the SMI driver itself.
  106. --- a/drivers/char/broadcom/Makefile
  107. +++ b/drivers/char/broadcom/Makefile
  108. @@ -3,4 +3,4 @@ obj-$(CONFIG_BCM2708_VCMEM) += vc_mem.o
  109. obj-$(CONFIG_BCM_VC_SM) += vc_sm/
  110. obj-$(CONFIG_BCM2835_DEVGPIOMEM)+= bcm2835-gpiomem.o
  111. -
  112. +obj-$(CONFIG_BCM2835_SMI_DEV) += bcm2835_smi_dev.o
  113. --- /dev/null
  114. +++ b/drivers/char/broadcom/bcm2835_smi_dev.c
  115. @@ -0,0 +1,402 @@
  116. +/**
  117. + * Character device driver for Broadcom Secondary Memory Interface
  118. + *
  119. + * Written by Luke Wren <luke@raspberrypi.org>
  120. + * Copyright (c) 2015, Raspberry Pi (Trading) Ltd.
  121. + *
  122. + * Redistribution and use in source and binary forms, with or without
  123. + * modification, are permitted provided that the following conditions
  124. + * are met:
  125. + * 1. Redistributions of source code must retain the above copyright
  126. + * notice, this list of conditions, and the following disclaimer,
  127. + * without modification.
  128. + * 2. Redistributions in binary form must reproduce the above copyright
  129. + * notice, this list of conditions and the following disclaimer in the
  130. + * documentation and/or other materials provided with the distribution.
  131. + * 3. The names of the above-listed copyright holders may not be used
  132. + * to endorse or promote products derived from this software without
  133. + * specific prior written permission.
  134. + *
  135. + * ALTERNATIVELY, this software may be distributed under the terms of the
  136. + * GNU General Public License ("GPL") version 2, as published by the Free
  137. + * Software Foundation.
  138. + *
  139. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  140. + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  141. + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  142. + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  143. + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  144. + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  145. + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  146. + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  147. + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  148. + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  149. + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  150. + */
  151. +
  152. +#include <linux/kernel.h>
  153. +#include <linux/module.h>
  154. +#include <linux/of.h>
  155. +#include <linux/platform_device.h>
  156. +#include <linux/slab.h>
  157. +#include <linux/mm.h>
  158. +#include <linux/pagemap.h>
  159. +#include <linux/fs.h>
  160. +#include <linux/cdev.h>
  161. +#include <linux/fs.h>
  162. +
  163. +#include <linux/broadcom/bcm2835_smi.h>
  164. +
  165. +#define DEVICE_NAME "bcm2835-smi-dev"
  166. +#define DRIVER_NAME "smi-dev-bcm2835"
  167. +#define DEVICE_MINOR 0
  168. +
  169. +static struct cdev bcm2835_smi_cdev;
  170. +static dev_t bcm2835_smi_devid;
  171. +static struct class *bcm2835_smi_class;
  172. +static struct device *bcm2835_smi_dev;
  173. +
  174. +struct bcm2835_smi_dev_instance {
  175. + struct device *dev;
  176. +};
  177. +
  178. +static struct bcm2835_smi_instance *smi_inst;
  179. +static struct bcm2835_smi_dev_instance *inst;
  180. +
  181. +static const char *const ioctl_names[] = {
  182. + "READ_SETTINGS",
  183. + "WRITE_SETTINGS",
  184. + "ADDRESS"
  185. +};
  186. +
  187. +/****************************************************************************
  188. +*
  189. +* SMI chardev file ops
  190. +*
  191. +***************************************************************************/
  192. +static long
  193. +bcm2835_smi_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
  194. +{
  195. + long ret = 0;
  196. +
  197. + dev_info(inst->dev, "serving ioctl...");
  198. +
  199. + switch (cmd) {
  200. + case BCM2835_SMI_IOC_GET_SETTINGS:{
  201. + struct smi_settings *settings;
  202. +
  203. + dev_info(inst->dev, "Reading SMI settings to user.");
  204. + settings = bcm2835_smi_get_settings_from_regs(smi_inst);
  205. + if (copy_to_user((void *)arg, settings,
  206. + sizeof(struct smi_settings)))
  207. + dev_err(inst->dev, "settings copy failed.");
  208. + break;
  209. + }
  210. + case BCM2835_SMI_IOC_WRITE_SETTINGS:{
  211. + struct smi_settings *settings;
  212. +
  213. + dev_info(inst->dev, "Setting user's SMI settings.");
  214. + settings = bcm2835_smi_get_settings_from_regs(smi_inst);
  215. + if (copy_from_user(settings, (void *)arg,
  216. + sizeof(struct smi_settings)))
  217. + dev_err(inst->dev, "settings copy failed.");
  218. + else
  219. + bcm2835_smi_set_regs_from_settings(smi_inst);
  220. + break;
  221. + }
  222. + case BCM2835_SMI_IOC_ADDRESS:
  223. + dev_info(inst->dev, "SMI address set: 0x%02x", (int)arg);
  224. + bcm2835_smi_set_address(smi_inst, arg);
  225. + break;
  226. + default:
  227. + dev_err(inst->dev, "invalid ioctl cmd: %d", cmd);
  228. + ret = -ENOTTY;
  229. + break;
  230. + }
  231. +
  232. + return ret;
  233. +}
  234. +
  235. +static int bcm2835_smi_open(struct inode *inode, struct file *file)
  236. +{
  237. + int dev = iminor(inode);
  238. +
  239. + dev_dbg(inst->dev, "SMI device opened.");
  240. +
  241. + if (dev != DEVICE_MINOR) {
  242. + dev_err(inst->dev,
  243. + "bcm2835_smi_release: Unknown minor device: %d",
  244. + dev);
  245. + return -ENXIO;
  246. + }
  247. +
  248. + return 0;
  249. +}
  250. +
  251. +static int bcm2835_smi_release(struct inode *inode, struct file *file)
  252. +{
  253. + int dev = iminor(inode);
  254. +
  255. + if (dev != DEVICE_MINOR) {
  256. + dev_err(inst->dev,
  257. + "bcm2835_smi_release: Unknown minor device %d", dev);
  258. + return -ENXIO;
  259. + }
  260. +
  261. + return 0;
  262. +}
  263. +
  264. +static ssize_t dma_bounce_user(
  265. + enum dma_transfer_direction dma_dir,
  266. + char __user *user_ptr,
  267. + size_t count,
  268. + struct bcm2835_smi_bounce_info *bounce)
  269. +{
  270. + int chunk_size;
  271. + int chunk_no = 0;
  272. + int count_left = count;
  273. +
  274. + while (count_left) {
  275. + int rv;
  276. + void *buf;
  277. +
  278. + /* Wait for current chunk to complete: */
  279. + if (down_timeout(&bounce->callback_sem,
  280. + msecs_to_jiffies(1000))) {
  281. + dev_err(inst->dev, "DMA bounce timed out");
  282. + count -= (count_left);
  283. + break;
  284. + }
  285. +
  286. + if (bounce->callback_sem.count >= DMA_BOUNCE_BUFFER_COUNT - 1)
  287. + dev_err(inst->dev, "WARNING: Ring buffer overflow");
  288. + chunk_size = count_left > DMA_BOUNCE_BUFFER_SIZE ?
  289. + DMA_BOUNCE_BUFFER_SIZE : count_left;
  290. + buf = bounce->buffer[chunk_no % DMA_BOUNCE_BUFFER_COUNT];
  291. + if (dma_dir == DMA_DEV_TO_MEM)
  292. + rv = copy_to_user(user_ptr, buf, chunk_size);
  293. + else
  294. + rv = copy_from_user(buf, user_ptr, chunk_size);
  295. + if (rv)
  296. + dev_err(inst->dev, "copy_*_user() failed!: %d", rv);
  297. + user_ptr += chunk_size;
  298. + count_left -= chunk_size;
  299. + chunk_no++;
  300. + }
  301. + return count;
  302. +}
  303. +
  304. +static ssize_t
  305. +bcm2835_read_file(struct file *f, char __user *user_ptr,
  306. + size_t count, loff_t *offs)
  307. +{
  308. + int odd_bytes;
  309. +
  310. + dev_dbg(inst->dev, "User reading %d bytes from SMI.", count);
  311. + /* We don't want to DMA a number of bytes % 4 != 0 (32 bit FIFO) */
  312. + if (count > DMA_THRESHOLD_BYTES)
  313. + odd_bytes = count & 0x3;
  314. + else
  315. + odd_bytes = count;
  316. + count -= odd_bytes;
  317. + if (count) {
  318. + struct bcm2835_smi_bounce_info *bounce;
  319. +
  320. + count = bcm2835_smi_user_dma(smi_inst,
  321. + DMA_DEV_TO_MEM, user_ptr, count,
  322. + &bounce);
  323. + if (count)
  324. + count = dma_bounce_user(DMA_DEV_TO_MEM, user_ptr,
  325. + count, bounce);
  326. + }
  327. + if (odd_bytes) {
  328. + /* Read from FIFO directly if not using DMA */
  329. + uint8_t buf[DMA_THRESHOLD_BYTES];
  330. +
  331. + bcm2835_smi_read_buf(smi_inst, buf, odd_bytes);
  332. + if (copy_to_user(user_ptr, buf, odd_bytes))
  333. + dev_err(inst->dev, "copy_to_user() failed.");
  334. + count += odd_bytes;
  335. +
  336. + }
  337. + return count;
  338. +}
  339. +
  340. +static ssize_t
  341. +bcm2835_write_file(struct file *f, const char __user *user_ptr,
  342. + size_t count, loff_t *offs)
  343. +{
  344. + int odd_bytes;
  345. +
  346. + dev_dbg(inst->dev, "User writing %d bytes to SMI.", count);
  347. + if (count > DMA_THRESHOLD_BYTES)
  348. + odd_bytes = count & 0x3;
  349. + else
  350. + odd_bytes = count;
  351. + count -= odd_bytes;
  352. + if (count) {
  353. + struct bcm2835_smi_bounce_info *bounce;
  354. +
  355. + count = bcm2835_smi_user_dma(smi_inst,
  356. + DMA_MEM_TO_DEV, (char __user *)user_ptr, count,
  357. + &bounce);
  358. + if (count)
  359. + count = dma_bounce_user(DMA_MEM_TO_DEV,
  360. + (char __user *)user_ptr,
  361. + count, bounce);
  362. + }
  363. + if (odd_bytes) {
  364. + uint8_t buf[DMA_THRESHOLD_BYTES];
  365. +
  366. + if (copy_from_user(buf, user_ptr, odd_bytes))
  367. + dev_err(inst->dev, "copy_from_user() failed.");
  368. + else
  369. + bcm2835_smi_write_buf(smi_inst, buf, odd_bytes);
  370. + count += odd_bytes;
  371. + }
  372. + return count;
  373. +}
  374. +
  375. +static const struct file_operations
  376. +bcm2835_smi_fops = {
  377. + .owner = THIS_MODULE,
  378. + .unlocked_ioctl = bcm2835_smi_ioctl,
  379. + .open = bcm2835_smi_open,
  380. + .release = bcm2835_smi_release,
  381. + .read = bcm2835_read_file,
  382. + .write = bcm2835_write_file,
  383. +};
  384. +
  385. +
  386. +/****************************************************************************
  387. +*
  388. +* bcm2835_smi_probe - called when the driver is loaded.
  389. +*
  390. +***************************************************************************/
  391. +
  392. +static int bcm2835_smi_dev_probe(struct platform_device *pdev)
  393. +{
  394. + int err;
  395. + void *ptr_err;
  396. + struct device *dev = &pdev->dev;
  397. + struct device_node *node = dev->of_node, *smi_node;
  398. +
  399. + if (!node) {
  400. + dev_err(dev, "No device tree node supplied!");
  401. + return -EINVAL;
  402. + }
  403. +
  404. + smi_node = of_parse_phandle(node, "smi_handle", 0);
  405. +
  406. + if (!smi_node) {
  407. + dev_err(dev, "No such property: smi_handle");
  408. + return -ENXIO;
  409. + }
  410. +
  411. + smi_inst = bcm2835_smi_get(smi_node);
  412. +
  413. + if (!smi_inst)
  414. + return -EPROBE_DEFER;
  415. +
  416. + /* Allocate buffers and instance data */
  417. +
  418. + inst = devm_kzalloc(dev, sizeof(*inst), GFP_KERNEL);
  419. +
  420. + if (!inst)
  421. + return -ENOMEM;
  422. +
  423. + inst->dev = dev;
  424. +
  425. + /* Create character device entries */
  426. +
  427. + err = alloc_chrdev_region(&bcm2835_smi_devid,
  428. + DEVICE_MINOR, 1, DEVICE_NAME);
  429. + if (err != 0) {
  430. + dev_err(inst->dev, "unable to allocate device number");
  431. + return -ENOMEM;
  432. + }
  433. + cdev_init(&bcm2835_smi_cdev, &bcm2835_smi_fops);
  434. + bcm2835_smi_cdev.owner = THIS_MODULE;
  435. + err = cdev_add(&bcm2835_smi_cdev, bcm2835_smi_devid, 1);
  436. + if (err != 0) {
  437. + dev_err(inst->dev, "unable to register device");
  438. + err = -ENOMEM;
  439. + goto failed_cdev_add;
  440. + }
  441. +
  442. + /* Create sysfs entries */
  443. +
  444. + bcm2835_smi_class = class_create(THIS_MODULE, DEVICE_NAME);
  445. + ptr_err = bcm2835_smi_class;
  446. + if (IS_ERR(ptr_err))
  447. + goto failed_class_create;
  448. +
  449. + bcm2835_smi_dev = device_create(bcm2835_smi_class, NULL,
  450. + bcm2835_smi_devid, NULL,
  451. + "smi");
  452. + ptr_err = bcm2835_smi_dev;
  453. + if (IS_ERR(ptr_err))
  454. + goto failed_device_create;
  455. +
  456. + dev_info(inst->dev, "initialised");
  457. +
  458. + return 0;
  459. +
  460. +failed_device_create:
  461. + class_destroy(bcm2835_smi_class);
  462. +failed_class_create:
  463. + cdev_del(&bcm2835_smi_cdev);
  464. + err = PTR_ERR(ptr_err);
  465. +failed_cdev_add:
  466. + unregister_chrdev_region(bcm2835_smi_devid, 1);
  467. + dev_err(dev, "could not load bcm2835_smi_dev");
  468. + return err;
  469. +}
  470. +
  471. +/****************************************************************************
  472. +*
  473. +* bcm2835_smi_remove - called when the driver is unloaded.
  474. +*
  475. +***************************************************************************/
  476. +
  477. +static int bcm2835_smi_dev_remove(struct platform_device *pdev)
  478. +{
  479. + device_destroy(bcm2835_smi_class, bcm2835_smi_devid);
  480. + class_destroy(bcm2835_smi_class);
  481. + cdev_del(&bcm2835_smi_cdev);
  482. + unregister_chrdev_region(bcm2835_smi_devid, 1);
  483. +
  484. + dev_info(inst->dev, "SMI character dev removed - OK");
  485. + return 0;
  486. +}
  487. +
  488. +/****************************************************************************
  489. +*
  490. +* Register the driver with device tree
  491. +*
  492. +***************************************************************************/
  493. +
  494. +static const struct of_device_id bcm2835_smi_dev_of_match[] = {
  495. + {.compatible = "brcm,bcm2835-smi-dev",},
  496. + { /* sentinel */ },
  497. +};
  498. +
  499. +MODULE_DEVICE_TABLE(of, bcm2835_smi_dev_of_match);
  500. +
  501. +static struct platform_driver bcm2835_smi_dev_driver = {
  502. + .probe = bcm2835_smi_dev_probe,
  503. + .remove = bcm2835_smi_dev_remove,
  504. + .driver = {
  505. + .name = DRIVER_NAME,
  506. + .owner = THIS_MODULE,
  507. + .of_match_table = bcm2835_smi_dev_of_match,
  508. + },
  509. +};
  510. +
  511. +module_platform_driver(bcm2835_smi_dev_driver);
  512. +
  513. +MODULE_ALIAS("platform:smi-dev-bcm2835");
  514. +MODULE_LICENSE("GPL");
  515. +MODULE_DESCRIPTION(
  516. + "Character device driver for BCM2835's secondary memory interface");
  517. +MODULE_AUTHOR("Luke Wren <luke@raspberrypi.org>");
  518. --- a/drivers/misc/Kconfig
  519. +++ b/drivers/misc/Kconfig
  520. @@ -10,6 +10,14 @@ config SENSORS_LIS3LV02D
  521. select INPUT_POLLDEV
  522. default n
  523. +config BCM2835_SMI
  524. + tristate "Broadcom 283x Secondary Memory Interface driver"
  525. + depends on MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835
  526. + default m
  527. + help
  528. + Driver for enabling and using Broadcom's Secondary/Slow Memory Interface.
  529. + Appears as /dev/bcm2835_smi. For ioctl interface see drivers/misc/bcm2835_smi.h
  530. +
  531. config AD525X_DPOT
  532. tristate "Analog Devices Digital Potentiometers"
  533. depends on (I2C || SPI) && SYSFS
  534. --- a/drivers/misc/Makefile
  535. +++ b/drivers/misc/Makefile
  536. @@ -9,6 +9,7 @@ obj-$(CONFIG_AD525X_DPOT_SPI) += ad525x_
  537. obj-$(CONFIG_INTEL_MID_PTI) += pti.o
  538. obj-$(CONFIG_ATMEL_SSC) += atmel-ssc.o
  539. obj-$(CONFIG_ATMEL_TCLIB) += atmel_tclib.o
  540. +obj-$(CONFIG_BCM2835_SMI) += bcm2835_smi.o
  541. obj-$(CONFIG_BMP085) += bmp085.o
  542. obj-$(CONFIG_BMP085_I2C) += bmp085-i2c.o
  543. obj-$(CONFIG_BMP085_SPI) += bmp085-spi.o
  544. --- /dev/null
  545. +++ b/drivers/misc/bcm2835_smi.c
  546. @@ -0,0 +1,985 @@
  547. +/**
  548. + * Broadcom Secondary Memory Interface driver
  549. + *
  550. + * Written by Luke Wren <luke@raspberrypi.org>
  551. + * Copyright (c) 2015, Raspberry Pi (Trading) Ltd.
  552. + *
  553. + * Redistribution and use in source and binary forms, with or without
  554. + * modification, are permitted provided that the following conditions
  555. + * are met:
  556. + * 1. Redistributions of source code must retain the above copyright
  557. + * notice, this list of conditions, and the following disclaimer,
  558. + * without modification.
  559. + * 2. Redistributions in binary form must reproduce the above copyright
  560. + * notice, this list of conditions and the following disclaimer in the
  561. + * documentation and/or other materials provided with the distribution.
  562. + * 3. The names of the above-listed copyright holders may not be used
  563. + * to endorse or promote products derived from this software without
  564. + * specific prior written permission.
  565. + *
  566. + * ALTERNATIVELY, this software may be distributed under the terms of the
  567. + * GNU General Public License ("GPL") version 2, as published by the Free
  568. + * Software Foundation.
  569. + *
  570. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  571. + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  572. + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  573. + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  574. + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  575. + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  576. + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  577. + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  578. + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  579. + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  580. + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  581. + */
  582. +
  583. +#include <linux/kernel.h>
  584. +#include <linux/module.h>
  585. +#include <linux/of.h>
  586. +#include <linux/platform_device.h>
  587. +#include <linux/of_address.h>
  588. +#include <linux/of_platform.h>
  589. +#include <linux/mm.h>
  590. +#include <linux/slab.h>
  591. +#include <linux/pagemap.h>
  592. +#include <linux/dma-mapping.h>
  593. +#include <linux/dmaengine.h>
  594. +#include <linux/semaphore.h>
  595. +#include <linux/spinlock.h>
  596. +#include <linux/io.h>
  597. +
  598. +#define BCM2835_SMI_IMPLEMENTATION
  599. +#include <linux/broadcom/bcm2835_smi.h>
  600. +
  601. +#define DRIVER_NAME "smi-bcm2835"
  602. +
  603. +#define N_PAGES_FROM_BYTES(n) ((n + PAGE_SIZE-1) / PAGE_SIZE)
  604. +
  605. +#define DMA_WRITE_TO_MEM true
  606. +#define DMA_READ_FROM_MEM false
  607. +
  608. +struct bcm2835_smi_instance {
  609. + struct device *dev;
  610. + struct smi_settings settings;
  611. + __iomem void *smi_regs_ptr, *cm_smi_regs_ptr;
  612. + dma_addr_t smi_regs_busaddr;
  613. +
  614. + struct dma_chan *dma_chan;
  615. + struct dma_slave_config dma_config;
  616. +
  617. + struct bcm2835_smi_bounce_info bounce;
  618. +
  619. + struct scatterlist buffer_sgl;
  620. +
  621. + int clock_source;
  622. + int clock_divisor;
  623. +
  624. + /* Sometimes we are called into in an atomic context (e.g. by
  625. + JFFS2 + MTD) so we can't use a mutex */
  626. + spinlock_t transaction_lock;
  627. +};
  628. +
  629. +/****************************************************************************
  630. +*
  631. +* SMI clock manager setup
  632. +*
  633. +***************************************************************************/
  634. +
  635. +static inline void write_smi_cm_reg(struct bcm2835_smi_instance *inst,
  636. + u32 val, unsigned reg)
  637. +{
  638. + writel(CM_PWD | val, inst->cm_smi_regs_ptr + reg);
  639. +}
  640. +
  641. +static inline u32 read_smi_cm_reg(struct bcm2835_smi_instance *inst,
  642. + unsigned reg)
  643. +{
  644. + return readl(inst->cm_smi_regs_ptr + reg);
  645. +}
  646. +
  647. +static void smi_setup_clock(struct bcm2835_smi_instance *inst)
  648. +{
  649. + dev_dbg(inst->dev, "Setting up clock...");
  650. + /* Disable SMI clock and wait for it to stop. */
  651. + write_smi_cm_reg(inst, 0, CM_SMI_CTL);
  652. + while (read_smi_cm_reg(inst, CM_SMI_CTL) & CM_SMI_CTL_BUSY)
  653. + ;
  654. +
  655. + write_smi_cm_reg(inst, (inst->clock_divisor << CM_SMI_DIV_DIVI_OFFS),
  656. + CM_SMI_DIV);
  657. + write_smi_cm_reg(inst, (inst->clock_source << CM_SMI_CTL_SRC_OFFS),
  658. + CM_SMI_CTL);
  659. +
  660. + /* Enable the clock */
  661. + write_smi_cm_reg(inst, (inst->clock_source << CM_SMI_CTL_SRC_OFFS) |
  662. + CM_SMI_CTL_ENAB, CM_SMI_CTL);
  663. +}
  664. +
  665. +/****************************************************************************
  666. +*
  667. +* SMI peripheral setup
  668. +*
  669. +***************************************************************************/
  670. +
  671. +static inline void write_smi_reg(struct bcm2835_smi_instance *inst,
  672. + u32 val, unsigned reg)
  673. +{
  674. + writel(val, inst->smi_regs_ptr + reg);
  675. +}
  676. +
  677. +static inline u32 read_smi_reg(struct bcm2835_smi_instance *inst, unsigned reg)
  678. +{
  679. + return readl(inst->smi_regs_ptr + reg);
  680. +}
  681. +
  682. +/* Token-paste macro for e.g SMIDSR_RSTROBE -> value of SMIDSR_RSTROBE_MASK */
  683. +#define _CONCAT(x, y) x##y
  684. +#define CONCAT(x, y) _CONCAT(x, y)
  685. +
  686. +#define SET_BIT_FIELD(dest, field, bits) ((dest) = \
  687. + ((dest) & ~CONCAT(field, _MASK)) | (((bits) << CONCAT(field, _OFFS))& \
  688. + CONCAT(field, _MASK)))
  689. +#define GET_BIT_FIELD(src, field) (((src) & \
  690. + CONCAT(field, _MASK)) >> CONCAT(field, _OFFS))
  691. +
  692. +static void smi_dump_context_labelled(struct bcm2835_smi_instance *inst,
  693. + const char *label)
  694. +{
  695. + dev_err(inst->dev, "SMI context dump: %s", label);
  696. + dev_err(inst->dev, "SMICS: 0x%08x", read_smi_reg(inst, SMICS));
  697. + dev_err(inst->dev, "SMIL: 0x%08x", read_smi_reg(inst, SMIL));
  698. + dev_err(inst->dev, "SMIDSR: 0x%08x", read_smi_reg(inst, SMIDSR0));
  699. + dev_err(inst->dev, "SMIDSW: 0x%08x", read_smi_reg(inst, SMIDSW0));
  700. + dev_err(inst->dev, "SMIDC: 0x%08x", read_smi_reg(inst, SMIDC));
  701. + dev_err(inst->dev, "SMIFD: 0x%08x", read_smi_reg(inst, SMIFD));
  702. + dev_err(inst->dev, " ");
  703. +}
  704. +
  705. +static inline void smi_dump_context(struct bcm2835_smi_instance *inst)
  706. +{
  707. + smi_dump_context_labelled(inst, "");
  708. +}
  709. +
  710. +static void smi_get_default_settings(struct bcm2835_smi_instance *inst)
  711. +{
  712. + struct smi_settings *settings = &inst->settings;
  713. +
  714. + settings->data_width = SMI_WIDTH_16BIT;
  715. + settings->pack_data = true;
  716. +
  717. + settings->read_setup_time = 1;
  718. + settings->read_hold_time = 1;
  719. + settings->read_pace_time = 1;
  720. + settings->read_strobe_time = 3;
  721. +
  722. + settings->write_setup_time = settings->read_setup_time;
  723. + settings->write_hold_time = settings->read_hold_time;
  724. + settings->write_pace_time = settings->read_pace_time;
  725. + settings->write_strobe_time = settings->read_strobe_time;
  726. +
  727. + settings->dma_enable = true;
  728. + settings->dma_passthrough_enable = false;
  729. + settings->dma_read_thresh = 0x01;
  730. + settings->dma_write_thresh = 0x3f;
  731. + settings->dma_panic_read_thresh = 0x20;
  732. + settings->dma_panic_write_thresh = 0x20;
  733. +}
  734. +
  735. +void bcm2835_smi_set_regs_from_settings(struct bcm2835_smi_instance *inst)
  736. +{
  737. + struct smi_settings *settings = &inst->settings;
  738. + int smidsr_temp = 0, smidsw_temp = 0, smics_temp,
  739. + smidcs_temp, smidc_temp = 0;
  740. +
  741. + spin_lock(&inst->transaction_lock);
  742. +
  743. + /* temporarily disable the peripheral: */
  744. + smics_temp = read_smi_reg(inst, SMICS);
  745. + write_smi_reg(inst, 0, SMICS);
  746. + smidcs_temp = read_smi_reg(inst, SMIDCS);
  747. + write_smi_reg(inst, 0, SMIDCS);
  748. +
  749. + if (settings->pack_data)
  750. + smics_temp |= SMICS_PXLDAT;
  751. + else
  752. + smics_temp &= ~SMICS_PXLDAT;
  753. +
  754. + SET_BIT_FIELD(smidsr_temp, SMIDSR_RWIDTH, settings->data_width);
  755. + SET_BIT_FIELD(smidsr_temp, SMIDSR_RSETUP, settings->read_setup_time);
  756. + SET_BIT_FIELD(smidsr_temp, SMIDSR_RHOLD, settings->read_hold_time);
  757. + SET_BIT_FIELD(smidsr_temp, SMIDSR_RPACE, settings->read_pace_time);
  758. + SET_BIT_FIELD(smidsr_temp, SMIDSR_RSTROBE, settings->read_strobe_time);
  759. + write_smi_reg(inst, smidsr_temp, SMIDSR0);
  760. +
  761. + SET_BIT_FIELD(smidsw_temp, SMIDSW_WWIDTH, settings->data_width);
  762. + if (settings->data_width == SMI_WIDTH_8BIT)
  763. + smidsw_temp |= SMIDSW_WSWAP;
  764. + else
  765. + smidsw_temp &= ~SMIDSW_WSWAP;
  766. + SET_BIT_FIELD(smidsw_temp, SMIDSW_WSETUP, settings->write_setup_time);
  767. + SET_BIT_FIELD(smidsw_temp, SMIDSW_WHOLD, settings->write_hold_time);
  768. + SET_BIT_FIELD(smidsw_temp, SMIDSW_WPACE, settings->write_pace_time);
  769. + SET_BIT_FIELD(smidsw_temp, SMIDSW_WSTROBE,
  770. + settings->write_strobe_time);
  771. + write_smi_reg(inst, smidsw_temp, SMIDSW0);
  772. +
  773. + SET_BIT_FIELD(smidc_temp, SMIDC_REQR, settings->dma_read_thresh);
  774. + SET_BIT_FIELD(smidc_temp, SMIDC_REQW, settings->dma_write_thresh);
  775. + SET_BIT_FIELD(smidc_temp, SMIDC_PANICR,
  776. + settings->dma_panic_read_thresh);
  777. + SET_BIT_FIELD(smidc_temp, SMIDC_PANICW,
  778. + settings->dma_panic_write_thresh);
  779. + if (settings->dma_passthrough_enable) {
  780. + smidc_temp |= SMIDC_DMAP;
  781. + smidsr_temp |= SMIDSR_RDREQ;
  782. + write_smi_reg(inst, smidsr_temp, SMIDSR0);
  783. + smidsw_temp |= SMIDSW_WDREQ;
  784. + write_smi_reg(inst, smidsw_temp, SMIDSW0);
  785. + } else
  786. + smidc_temp &= ~SMIDC_DMAP;
  787. + if (settings->dma_enable)
  788. + smidc_temp |= SMIDC_DMAEN;
  789. + else
  790. + smidc_temp &= ~SMIDC_DMAEN;
  791. +
  792. + write_smi_reg(inst, smidc_temp, SMIDC);
  793. +
  794. + /* re-enable (if was previously enabled) */
  795. + write_smi_reg(inst, smics_temp, SMICS);
  796. + write_smi_reg(inst, smidcs_temp, SMIDCS);
  797. +
  798. + spin_unlock(&inst->transaction_lock);
  799. +}
  800. +EXPORT_SYMBOL(bcm2835_smi_set_regs_from_settings);
  801. +
  802. +struct smi_settings *bcm2835_smi_get_settings_from_regs
  803. + (struct bcm2835_smi_instance *inst)
  804. +{
  805. + struct smi_settings *settings = &inst->settings;
  806. + int smidsr, smidsw, smidc;
  807. +
  808. + spin_lock(&inst->transaction_lock);
  809. +
  810. + smidsr = read_smi_reg(inst, SMIDSR0);
  811. + smidsw = read_smi_reg(inst, SMIDSW0);
  812. + smidc = read_smi_reg(inst, SMIDC);
  813. +
  814. + settings->pack_data = (read_smi_reg(inst, SMICS) & SMICS_PXLDAT) ?
  815. + true : false;
  816. +
  817. + settings->data_width = GET_BIT_FIELD(smidsr, SMIDSR_RWIDTH);
  818. + settings->read_setup_time = GET_BIT_FIELD(smidsr, SMIDSR_RSETUP);
  819. + settings->read_hold_time = GET_BIT_FIELD(smidsr, SMIDSR_RHOLD);
  820. + settings->read_pace_time = GET_BIT_FIELD(smidsr, SMIDSR_RPACE);
  821. + settings->read_strobe_time = GET_BIT_FIELD(smidsr, SMIDSR_RSTROBE);
  822. +
  823. + settings->write_setup_time = GET_BIT_FIELD(smidsw, SMIDSW_WSETUP);
  824. + settings->write_hold_time = GET_BIT_FIELD(smidsw, SMIDSW_WHOLD);
  825. + settings->write_pace_time = GET_BIT_FIELD(smidsw, SMIDSW_WPACE);
  826. + settings->write_strobe_time = GET_BIT_FIELD(smidsw, SMIDSW_WSTROBE);
  827. +
  828. + settings->dma_read_thresh = GET_BIT_FIELD(smidc, SMIDC_REQR);
  829. + settings->dma_write_thresh = GET_BIT_FIELD(smidc, SMIDC_REQW);
  830. + settings->dma_panic_read_thresh = GET_BIT_FIELD(smidc, SMIDC_PANICR);
  831. + settings->dma_panic_write_thresh = GET_BIT_FIELD(smidc, SMIDC_PANICW);
  832. + settings->dma_passthrough_enable = (smidc & SMIDC_DMAP) ? true : false;
  833. + settings->dma_enable = (smidc & SMIDC_DMAEN) ? true : false;
  834. +
  835. + spin_unlock(&inst->transaction_lock);
  836. +
  837. + return settings;
  838. +}
  839. +EXPORT_SYMBOL(bcm2835_smi_get_settings_from_regs);
  840. +
  841. +static inline void smi_set_address(struct bcm2835_smi_instance *inst,
  842. + unsigned int address)
  843. +{
  844. + int smia_temp = 0, smida_temp = 0;
  845. +
  846. + SET_BIT_FIELD(smia_temp, SMIA_ADDR, address);
  847. + SET_BIT_FIELD(smida_temp, SMIDA_ADDR, address);
  848. +
  849. + /* Write to both address registers - user doesn't care whether we're
  850. + doing programmed or direct transfers. */
  851. + write_smi_reg(inst, smia_temp, SMIA);
  852. + write_smi_reg(inst, smida_temp, SMIDA);
  853. +}
  854. +
  855. +static void smi_setup_regs(struct bcm2835_smi_instance *inst)
  856. +{
  857. +
  858. + dev_dbg(inst->dev, "Initialising SMI registers...");
  859. + /* Disable the peripheral if already enabled */
  860. + write_smi_reg(inst, 0, SMICS);
  861. + write_smi_reg(inst, 0, SMIDCS);
  862. +
  863. + smi_get_default_settings(inst);
  864. + bcm2835_smi_set_regs_from_settings(inst);
  865. + smi_set_address(inst, 0);
  866. +
  867. + write_smi_reg(inst, read_smi_reg(inst, SMICS) | SMICS_ENABLE, SMICS);
  868. + write_smi_reg(inst, read_smi_reg(inst, SMIDCS) | SMIDCS_ENABLE,
  869. + SMIDCS);
  870. +}
  871. +
  872. +/****************************************************************************
  873. +*
  874. +* Low-level SMI access functions
  875. +* Other modules should use the exported higher-level functions e.g.
  876. +* bcm2835_smi_write_buf() unless they have a good reason to use these
  877. +*
  878. +***************************************************************************/
  879. +
  880. +static inline uint32_t smi_read_single_word(struct bcm2835_smi_instance *inst)
  881. +{
  882. + int timeout = 0;
  883. +
  884. + write_smi_reg(inst, SMIDCS_ENABLE, SMIDCS);
  885. + write_smi_reg(inst, SMIDCS_ENABLE | SMIDCS_START, SMIDCS);
  886. + /* Make sure things happen in the right order...*/
  887. + mb();
  888. + while (!(read_smi_reg(inst, SMIDCS) & SMIDCS_DONE) &&
  889. + ++timeout < 10000)
  890. + ;
  891. + if (timeout < 10000)
  892. + return read_smi_reg(inst, SMIDD);
  893. +
  894. + dev_err(inst->dev,
  895. + "SMI direct read timed out (is the clock set up correctly?)");
  896. + return 0;
  897. +}
  898. +
  899. +static inline void smi_write_single_word(struct bcm2835_smi_instance *inst,
  900. + uint32_t data)
  901. +{
  902. + int timeout = 0;
  903. +
  904. + write_smi_reg(inst, SMIDCS_ENABLE | SMIDCS_WRITE, SMIDCS);
  905. + write_smi_reg(inst, data, SMIDD);
  906. + write_smi_reg(inst, SMIDCS_ENABLE | SMIDCS_WRITE | SMIDCS_START,
  907. + SMIDCS);
  908. +
  909. + while (!(read_smi_reg(inst, SMIDCS) & SMIDCS_DONE) &&
  910. + ++timeout < 10000)
  911. + ;
  912. + if (timeout >= 10000)
  913. + dev_err(inst->dev,
  914. + "SMI direct write timed out (is the clock set up correctly?)");
  915. +}
  916. +
  917. +/* Initiates a programmed read into the read FIFO. It is up to the caller to
  918. + * read data from the FIFO - either via paced DMA transfer,
  919. + * or polling SMICS_RXD to check whether data is available.
  920. + * SMICS_ACTIVE will go low upon completion. */
  921. +static void smi_init_programmed_read(struct bcm2835_smi_instance *inst,
  922. + int num_transfers)
  923. +{
  924. + int smics_temp;
  925. +
  926. + /* Disable the peripheral: */
  927. + smics_temp = read_smi_reg(inst, SMICS) & ~(SMICS_ENABLE | SMICS_WRITE);
  928. + write_smi_reg(inst, smics_temp, SMICS);
  929. + while (read_smi_reg(inst, SMICS) & SMICS_ENABLE)
  930. + ;
  931. +
  932. + /* Program the transfer count: */
  933. + write_smi_reg(inst, num_transfers, SMIL);
  934. +
  935. + /* re-enable and start: */
  936. + smics_temp |= SMICS_ENABLE;
  937. + write_smi_reg(inst, smics_temp, SMICS);
  938. + smics_temp |= SMICS_CLEAR;
  939. + /* Just to be certain: */
  940. + mb();
  941. + while (read_smi_reg(inst, SMICS) & SMICS_ACTIVE)
  942. + ;
  943. + write_smi_reg(inst, smics_temp, SMICS);
  944. + smics_temp |= SMICS_START;
  945. + write_smi_reg(inst, smics_temp, SMICS);
  946. +}
  947. +
  948. +/* Initiates a programmed write sequence, using data from the write FIFO.
  949. + * It is up to the caller to initiate a DMA transfer before calling,
  950. + * or use another method to keep the write FIFO topped up.
  951. + * SMICS_ACTIVE will go low upon completion.
  952. + */
  953. +static void smi_init_programmed_write(struct bcm2835_smi_instance *inst,
  954. + int num_transfers)
  955. +{
  956. + int smics_temp;
  957. +
  958. + /* Disable the peripheral: */
  959. + smics_temp = read_smi_reg(inst, SMICS) & ~SMICS_ENABLE;
  960. + write_smi_reg(inst, smics_temp, SMICS);
  961. + while (read_smi_reg(inst, SMICS) & SMICS_ENABLE)
  962. + ;
  963. +
  964. + /* Program the transfer count: */
  965. + write_smi_reg(inst, num_transfers, SMIL);
  966. +
  967. + /* setup, re-enable and start: */
  968. + smics_temp |= SMICS_WRITE | SMICS_ENABLE;
  969. + write_smi_reg(inst, smics_temp, SMICS);
  970. + smics_temp |= SMICS_START;
  971. + write_smi_reg(inst, smics_temp, SMICS);
  972. +}
  973. +
  974. +/* Initiate a read and then poll FIFO for data, reading out as it appears. */
  975. +static void smi_read_fifo(struct bcm2835_smi_instance *inst,
  976. + uint32_t *dest, int n_bytes)
  977. +{
  978. + if (read_smi_reg(inst, SMICS) & SMICS_RXD) {
  979. + smi_dump_context_labelled(inst,
  980. + "WARNING: read FIFO not empty at start of read call.");
  981. + while (read_smi_reg(inst, SMICS))
  982. + ;
  983. + }
  984. +
  985. + /* Dispatch the read: */
  986. + if (inst->settings.data_width == SMI_WIDTH_8BIT)
  987. + smi_init_programmed_read(inst, n_bytes);
  988. + else if (inst->settings.data_width == SMI_WIDTH_16BIT)
  989. + smi_init_programmed_read(inst, n_bytes / 2);
  990. + else {
  991. + dev_err(inst->dev, "Unsupported data width for read.");
  992. + return;
  993. + }
  994. +
  995. + /* Poll FIFO to keep it empty */
  996. + while (!(read_smi_reg(inst, SMICS) & SMICS_DONE))
  997. + if (read_smi_reg(inst, SMICS) & SMICS_RXD)
  998. + *dest++ = read_smi_reg(inst, SMID);
  999. +
  1000. + /* Ensure that the FIFO is emptied */
  1001. + if (read_smi_reg(inst, SMICS) & SMICS_RXD) {
  1002. + int fifo_count;
  1003. +
  1004. + fifo_count = GET_BIT_FIELD(read_smi_reg(inst, SMIFD),
  1005. + SMIFD_FCNT);
  1006. + while (fifo_count--)
  1007. + *dest++ = read_smi_reg(inst, SMID);
  1008. + }
  1009. +
  1010. + if (!(read_smi_reg(inst, SMICS) & SMICS_DONE))
  1011. + smi_dump_context_labelled(inst,
  1012. + "WARNING: transaction finished but done bit not set.");
  1013. +
  1014. + if (read_smi_reg(inst, SMICS) & SMICS_RXD)
  1015. + smi_dump_context_labelled(inst,
  1016. + "WARNING: read FIFO not empty at end of read call.");
  1017. +
  1018. +}
  1019. +
  1020. +/* Initiate a write, and then keep the FIFO topped up. */
  1021. +static void smi_write_fifo(struct bcm2835_smi_instance *inst,
  1022. + uint32_t *src, int n_bytes)
  1023. +{
  1024. + int i, timeout = 0;
  1025. +
  1026. + /* Empty FIFOs if not already so */
  1027. + if (!(read_smi_reg(inst, SMICS) & SMICS_TXE)) {
  1028. + smi_dump_context_labelled(inst,
  1029. + "WARNING: write fifo not empty at start of write call.");
  1030. + write_smi_reg(inst, read_smi_reg(inst, SMICS) | SMICS_CLEAR,
  1031. + SMICS);
  1032. + }
  1033. +
  1034. + /* Initiate the transfer */
  1035. + if (inst->settings.data_width == SMI_WIDTH_8BIT)
  1036. + smi_init_programmed_write(inst, n_bytes);
  1037. + else if (inst->settings.data_width == SMI_WIDTH_16BIT)
  1038. + smi_init_programmed_write(inst, n_bytes / 2);
  1039. + else {
  1040. + dev_err(inst->dev, "Unsupported data width for write.");
  1041. + return;
  1042. + }
  1043. + /* Fill the FIFO: */
  1044. + for (i = 0; i < (n_bytes - 1) / 4 + 1; ++i) {
  1045. + while (!(read_smi_reg(inst, SMICS) & SMICS_TXD))
  1046. + ;
  1047. + write_smi_reg(inst, *src++, SMID);
  1048. + }
  1049. + /* Busy wait... */
  1050. + while (!(read_smi_reg(inst, SMICS) & SMICS_DONE) && ++timeout <
  1051. + 1000000)
  1052. + ;
  1053. + if (timeout >= 1000000)
  1054. + smi_dump_context_labelled(inst,
  1055. + "Timed out on write operation!");
  1056. + if (!(read_smi_reg(inst, SMICS) & SMICS_TXE))
  1057. + smi_dump_context_labelled(inst,
  1058. + "WARNING: FIFO not empty at end of write operation.");
  1059. +}
  1060. +
  1061. +/****************************************************************************
  1062. +*
  1063. +* SMI DMA operations
  1064. +*
  1065. +***************************************************************************/
  1066. +
  1067. +/* Disable SMI and put it into the correct direction before doing DMA setup.
  1068. + Stops spurious DREQs during setup. Peripheral is re-enabled by init_*() */
  1069. +static void smi_disable(struct bcm2835_smi_instance *inst,
  1070. + enum dma_transfer_direction direction)
  1071. +{
  1072. + int smics_temp = read_smi_reg(inst, SMICS) & ~SMICS_ENABLE;
  1073. +
  1074. + if (direction == DMA_DEV_TO_MEM)
  1075. + smics_temp &= ~SMICS_WRITE;
  1076. + else
  1077. + smics_temp |= SMICS_WRITE;
  1078. + write_smi_reg(inst, smics_temp, SMICS);
  1079. + while (read_smi_reg(inst, SMICS) & SMICS_ACTIVE)
  1080. + ;
  1081. +}
  1082. +
  1083. +static struct scatterlist *smi_scatterlist_from_buffer(
  1084. + struct bcm2835_smi_instance *inst,
  1085. + dma_addr_t buf,
  1086. + size_t len,
  1087. + struct scatterlist *sg)
  1088. +{
  1089. + sg_init_table(sg, 1);
  1090. + sg_dma_address(sg) = buf;
  1091. + sg_dma_len(sg) = len;
  1092. + return sg;
  1093. +}
  1094. +
  1095. +static void smi_dma_callback_user_copy(void *param)
  1096. +{
  1097. + /* Notify the bottom half that a chunk is ready for user copy */
  1098. + struct bcm2835_smi_instance *inst =
  1099. + (struct bcm2835_smi_instance *)param;
  1100. +
  1101. + up(&inst->bounce.callback_sem);
  1102. +}
  1103. +
  1104. +/* Creates a descriptor, assigns the given callback, and submits the
  1105. + descriptor to dmaengine. Does not block - can queue up multiple
  1106. + descriptors and then wait for them all to complete.
  1107. + sg_len is the number of control blocks, NOT the number of bytes.
  1108. + dir can be DMA_MEM_TO_DEV or DMA_DEV_TO_MEM.
  1109. + callback can be NULL - in this case it is not called. */
  1110. +static inline struct dma_async_tx_descriptor *smi_dma_submit_sgl(
  1111. + struct bcm2835_smi_instance *inst,
  1112. + struct scatterlist *sgl,
  1113. + size_t sg_len,
  1114. + enum dma_transfer_direction dir,
  1115. + dma_async_tx_callback callback)
  1116. +{
  1117. + struct dma_async_tx_descriptor *desc;
  1118. +
  1119. + desc = dmaengine_prep_slave_sg(inst->dma_chan,
  1120. + sgl,
  1121. + sg_len,
  1122. + dir,
  1123. + DMA_PREP_INTERRUPT | DMA_CTRL_ACK |
  1124. + DMA_PREP_FENCE);
  1125. + if (!desc) {
  1126. + dev_err(inst->dev, "read_sgl: dma slave preparation failed!");
  1127. + write_smi_reg(inst, read_smi_reg(inst, SMICS) & ~SMICS_ACTIVE,
  1128. + SMICS);
  1129. + while (read_smi_reg(inst, SMICS) & SMICS_ACTIVE)
  1130. + cpu_relax();
  1131. + write_smi_reg(inst, read_smi_reg(inst, SMICS) | SMICS_ACTIVE,
  1132. + SMICS);
  1133. + return NULL;
  1134. + }
  1135. + desc->callback = callback;
  1136. + desc->callback_param = inst;
  1137. + if (dmaengine_submit(desc) < 0)
  1138. + return NULL;
  1139. + return desc;
  1140. +}
  1141. +
  1142. +/* NB this function blocks until the transfer is complete */
  1143. +static void
  1144. +smi_dma_read_sgl(struct bcm2835_smi_instance *inst,
  1145. + struct scatterlist *sgl, size_t sg_len, size_t n_bytes)
  1146. +{
  1147. + struct dma_async_tx_descriptor *desc;
  1148. +
  1149. + /* Disable SMI and set to read before dispatching DMA - if SMI is in
  1150. + * write mode and TX fifo is empty, it will generate a DREQ which may
  1151. + * cause the read DMA to complete before the SMI read command is even
  1152. + * dispatched! We want to dispatch DMA before SMI read so that reading
  1153. + * is gapless, for logic analyser.
  1154. + */
  1155. +
  1156. + smi_disable(inst, DMA_DEV_TO_MEM);
  1157. +
  1158. + desc = smi_dma_submit_sgl(inst, sgl, sg_len, DMA_DEV_TO_MEM, NULL);
  1159. + dma_async_issue_pending(inst->dma_chan);
  1160. +
  1161. + if (inst->settings.data_width == SMI_WIDTH_8BIT)
  1162. + smi_init_programmed_read(inst, n_bytes);
  1163. + else
  1164. + smi_init_programmed_read(inst, n_bytes / 2);
  1165. +
  1166. + if (dma_wait_for_async_tx(desc) == DMA_ERROR)
  1167. + smi_dump_context_labelled(inst, "DMA timeout!");
  1168. +}
  1169. +
  1170. +static void
  1171. +smi_dma_write_sgl(struct bcm2835_smi_instance *inst,
  1172. + struct scatterlist *sgl, size_t sg_len, size_t n_bytes)
  1173. +{
  1174. + struct dma_async_tx_descriptor *desc;
  1175. +
  1176. + if (inst->settings.data_width == SMI_WIDTH_8BIT)
  1177. + smi_init_programmed_write(inst, n_bytes);
  1178. + else
  1179. + smi_init_programmed_write(inst, n_bytes / 2);
  1180. +
  1181. + desc = smi_dma_submit_sgl(inst, sgl, sg_len, DMA_MEM_TO_DEV, NULL);
  1182. + dma_async_issue_pending(inst->dma_chan);
  1183. +
  1184. + if (dma_wait_for_async_tx(desc) == DMA_ERROR)
  1185. + smi_dump_context_labelled(inst, "DMA timeout!");
  1186. + else
  1187. + /* Wait for SMI to finish our writes */
  1188. + while (!(read_smi_reg(inst, SMICS) & SMICS_DONE))
  1189. + cpu_relax();
  1190. +}
  1191. +
  1192. +ssize_t bcm2835_smi_user_dma(
  1193. + struct bcm2835_smi_instance *inst,
  1194. + enum dma_transfer_direction dma_dir,
  1195. + char __user *user_ptr, size_t count,
  1196. + struct bcm2835_smi_bounce_info **bounce)
  1197. +{
  1198. + int chunk_no = 0, chunk_size, count_left = count;
  1199. + struct scatterlist *sgl;
  1200. + void (*init_trans_func)(struct bcm2835_smi_instance *, int);
  1201. +
  1202. + spin_lock(&inst->transaction_lock);
  1203. +
  1204. + if (dma_dir == DMA_DEV_TO_MEM)
  1205. + init_trans_func = smi_init_programmed_read;
  1206. + else
  1207. + init_trans_func = smi_init_programmed_write;
  1208. +
  1209. + smi_disable(inst, dma_dir);
  1210. +
  1211. + sema_init(&inst->bounce.callback_sem, 0);
  1212. + if (bounce)
  1213. + *bounce = &inst->bounce;
  1214. + while (count_left) {
  1215. + chunk_size = count_left > DMA_BOUNCE_BUFFER_SIZE ?
  1216. + DMA_BOUNCE_BUFFER_SIZE : count_left;
  1217. + if (chunk_size == DMA_BOUNCE_BUFFER_SIZE) {
  1218. + sgl =
  1219. + &inst->bounce.sgl[chunk_no % DMA_BOUNCE_BUFFER_COUNT];
  1220. + } else {
  1221. + sgl = smi_scatterlist_from_buffer(
  1222. + inst,
  1223. + inst->bounce.phys[
  1224. + chunk_no % DMA_BOUNCE_BUFFER_COUNT],
  1225. + chunk_size,
  1226. + &inst->buffer_sgl);
  1227. + }
  1228. +
  1229. + if (!smi_dma_submit_sgl(inst, sgl, 1, dma_dir,
  1230. + smi_dma_callback_user_copy
  1231. + )) {
  1232. + dev_err(inst->dev, "sgl submit failed");
  1233. + count = 0;
  1234. + goto out;
  1235. + }
  1236. + count_left -= chunk_size;
  1237. + chunk_no++;
  1238. + }
  1239. + dma_async_issue_pending(inst->dma_chan);
  1240. +
  1241. + if (inst->settings.data_width == SMI_WIDTH_8BIT)
  1242. + init_trans_func(inst, count);
  1243. + else if (inst->settings.data_width == SMI_WIDTH_16BIT)
  1244. + init_trans_func(inst, count / 2);
  1245. +out:
  1246. + spin_unlock(&inst->transaction_lock);
  1247. + return count;
  1248. +}
  1249. +EXPORT_SYMBOL(bcm2835_smi_user_dma);
  1250. +
  1251. +
  1252. +/****************************************************************************
  1253. +*
  1254. +* High level buffer transfer functions - for use by other drivers
  1255. +*
  1256. +***************************************************************************/
  1257. +
  1258. +/* Buffer must be physically contiguous - i.e. kmalloc, not vmalloc! */
  1259. +void bcm2835_smi_write_buf(
  1260. + struct bcm2835_smi_instance *inst,
  1261. + const void *buf, size_t n_bytes)
  1262. +{
  1263. + int odd_bytes = n_bytes & 0x3;
  1264. +
  1265. + n_bytes -= odd_bytes;
  1266. +
  1267. + spin_lock(&inst->transaction_lock);
  1268. +
  1269. + if (n_bytes > DMA_THRESHOLD_BYTES) {
  1270. + dma_addr_t phy_addr = dma_map_single(
  1271. + inst->dev,
  1272. + (void *)buf,
  1273. + n_bytes,
  1274. + DMA_MEM_TO_DEV);
  1275. + struct scatterlist *sgl =
  1276. + smi_scatterlist_from_buffer(inst, phy_addr, n_bytes,
  1277. + &inst->buffer_sgl);
  1278. +
  1279. + if (!sgl) {
  1280. + smi_dump_context_labelled(inst,
  1281. + "Error: could not create scatterlist for write!");
  1282. + goto out;
  1283. + }
  1284. + smi_dma_write_sgl(inst, sgl, 1, n_bytes);
  1285. +
  1286. + dma_unmap_single
  1287. + (inst->dev, phy_addr, n_bytes, DMA_MEM_TO_DEV);
  1288. + } else if (n_bytes) {
  1289. + smi_write_fifo(inst, (uint32_t *) buf, n_bytes);
  1290. + }
  1291. + buf += n_bytes;
  1292. +
  1293. + if (inst->settings.data_width == SMI_WIDTH_8BIT) {
  1294. + while (odd_bytes--)
  1295. + smi_write_single_word(inst, *(uint8_t *) (buf++));
  1296. + } else {
  1297. + while (odd_bytes >= 2) {
  1298. + smi_write_single_word(inst, *(uint16_t *)buf);
  1299. + buf += 2;
  1300. + odd_bytes -= 2;
  1301. + }
  1302. + if (odd_bytes) {
  1303. + /* Reading an odd number of bytes on a 16 bit bus is
  1304. + a user bug. It's kinder to fail early and tell them
  1305. + than to e.g. transparently give them the bottom byte
  1306. + of a 16 bit transfer. */
  1307. + dev_err(inst->dev,
  1308. + "WARNING: odd number of bytes specified for wide transfer.");
  1309. + dev_err(inst->dev,
  1310. + "At least one byte dropped as a result.");
  1311. + dump_stack();
  1312. + }
  1313. + }
  1314. +out:
  1315. + spin_unlock(&inst->transaction_lock);
  1316. +}
  1317. +EXPORT_SYMBOL(bcm2835_smi_write_buf);
  1318. +
  1319. +void bcm2835_smi_read_buf(struct bcm2835_smi_instance *inst,
  1320. + void *buf, size_t n_bytes)
  1321. +{
  1322. +
  1323. + /* SMI is inherently 32-bit, which causes surprising amounts of mess
  1324. + for bytes % 4 != 0. Easiest to avoid this mess altogether
  1325. + by handling remainder separately. */
  1326. + int odd_bytes = n_bytes & 0x3;
  1327. +
  1328. + spin_lock(&inst->transaction_lock);
  1329. + n_bytes -= odd_bytes;
  1330. + if (n_bytes > DMA_THRESHOLD_BYTES) {
  1331. + dma_addr_t phy_addr = dma_map_single(inst->dev,
  1332. + buf, n_bytes,
  1333. + DMA_DEV_TO_MEM);
  1334. + struct scatterlist *sgl = smi_scatterlist_from_buffer(
  1335. + inst, phy_addr, n_bytes,
  1336. + &inst->buffer_sgl);
  1337. + if (!sgl) {
  1338. + smi_dump_context_labelled(inst,
  1339. + "Error: could not create scatterlist for read!");
  1340. + goto out;
  1341. + }
  1342. + smi_dma_read_sgl(inst, sgl, 1, n_bytes);
  1343. + dma_unmap_single(inst->dev, phy_addr, n_bytes, DMA_DEV_TO_MEM);
  1344. + } else if (n_bytes) {
  1345. + smi_read_fifo(inst, (uint32_t *)buf, n_bytes);
  1346. + }
  1347. + buf += n_bytes;
  1348. +
  1349. + if (inst->settings.data_width == SMI_WIDTH_8BIT) {
  1350. + while (odd_bytes--)
  1351. + *((uint8_t *) (buf++)) = smi_read_single_word(inst);
  1352. + } else {
  1353. + while (odd_bytes >= 2) {
  1354. + *(uint16_t *) buf = smi_read_single_word(inst);
  1355. + buf += 2;
  1356. + odd_bytes -= 2;
  1357. + }
  1358. + if (odd_bytes) {
  1359. + dev_err(inst->dev,
  1360. + "WARNING: odd number of bytes specified for wide transfer.");
  1361. + dev_err(inst->dev,
  1362. + "At least one byte dropped as a result.");
  1363. + dump_stack();
  1364. + }
  1365. + }
  1366. +out:
  1367. + spin_unlock(&inst->transaction_lock);
  1368. +}
  1369. +EXPORT_SYMBOL(bcm2835_smi_read_buf);
  1370. +
  1371. +void bcm2835_smi_set_address(struct bcm2835_smi_instance *inst,
  1372. + unsigned int address)
  1373. +{
  1374. + spin_lock(&inst->transaction_lock);
  1375. + smi_set_address(inst, address);
  1376. + spin_unlock(&inst->transaction_lock);
  1377. +}
  1378. +EXPORT_SYMBOL(bcm2835_smi_set_address);
  1379. +
  1380. +struct bcm2835_smi_instance *bcm2835_smi_get(struct device_node *node)
  1381. +{
  1382. + struct platform_device *pdev;
  1383. +
  1384. + if (!node)
  1385. + return NULL;
  1386. +
  1387. + pdev = of_find_device_by_node(node);
  1388. + if (!pdev)
  1389. + return NULL;
  1390. +
  1391. + return platform_get_drvdata(pdev);
  1392. +}
  1393. +EXPORT_SYMBOL(bcm2835_smi_get);
  1394. +
  1395. +/****************************************************************************
  1396. +*
  1397. +* bcm2835_smi_probe - called when the driver is loaded.
  1398. +*
  1399. +***************************************************************************/
  1400. +
  1401. +static int bcm2835_smi_dma_setup(struct bcm2835_smi_instance *inst)
  1402. +{
  1403. + int i, rv = 0;
  1404. +
  1405. + inst->dma_chan = dma_request_slave_channel(inst->dev, "rx-tx");
  1406. +
  1407. + inst->dma_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  1408. + inst->dma_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  1409. + inst->dma_config.src_addr = inst->smi_regs_busaddr + SMID;
  1410. + inst->dma_config.dst_addr = inst->dma_config.src_addr;
  1411. + /* Direction unimportant - always overridden by prep_slave_sg */
  1412. + inst->dma_config.direction = DMA_DEV_TO_MEM;
  1413. + dmaengine_slave_config(inst->dma_chan, &inst->dma_config);
  1414. + /* Alloc and map bounce buffers */
  1415. + for (i = 0; i < DMA_BOUNCE_BUFFER_COUNT; ++i) {
  1416. + inst->bounce.buffer[i] =
  1417. + dmam_alloc_coherent(inst->dev, DMA_BOUNCE_BUFFER_SIZE,
  1418. + &inst->bounce.phys[i],
  1419. + GFP_KERNEL);
  1420. + if (!inst->bounce.buffer[i]) {
  1421. + dev_err(inst->dev, "Could not allocate buffer!");
  1422. + rv = -ENOMEM;
  1423. + break;
  1424. + }
  1425. + smi_scatterlist_from_buffer(
  1426. + inst,
  1427. + inst->bounce.phys[i],
  1428. + DMA_BOUNCE_BUFFER_SIZE,
  1429. + &inst->bounce.sgl[i]
  1430. + );
  1431. + }
  1432. +
  1433. + return rv;
  1434. +}
  1435. +
  1436. +static int bcm2835_smi_probe(struct platform_device *pdev)
  1437. +{
  1438. + int err;
  1439. + struct device *dev = &pdev->dev;
  1440. + struct device_node *node = dev->of_node;
  1441. + struct resource *ioresource;
  1442. + struct bcm2835_smi_instance *inst;
  1443. +
  1444. + /* Allocate buffers and instance data */
  1445. +
  1446. + inst = devm_kzalloc(dev, sizeof(struct bcm2835_smi_instance),
  1447. + GFP_KERNEL);
  1448. +
  1449. + if (!inst)
  1450. + return -ENOMEM;
  1451. +
  1452. + inst->dev = dev;
  1453. + spin_lock_init(&inst->transaction_lock);
  1454. +
  1455. + /* We require device tree support */
  1456. + if (!node)
  1457. + return -EINVAL;
  1458. +
  1459. + ioresource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1460. + inst->smi_regs_ptr = devm_ioremap_resource(dev, ioresource);
  1461. + ioresource = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  1462. + inst->cm_smi_regs_ptr = devm_ioremap_resource(dev, ioresource);
  1463. + inst->smi_regs_busaddr = be32_to_cpu(
  1464. + *of_get_address(node, 0, NULL, NULL));
  1465. + of_property_read_u32(node,
  1466. + "brcm,smi-clock-source",
  1467. + &inst->clock_source);
  1468. + of_property_read_u32(node,
  1469. + "brcm,smi-clock-divisor",
  1470. + &inst->clock_divisor);
  1471. +
  1472. + err = bcm2835_smi_dma_setup(inst);
  1473. + if (err)
  1474. + return err;
  1475. +
  1476. + /* Finally, do peripheral setup */
  1477. +
  1478. + smi_setup_clock(inst);
  1479. + smi_setup_regs(inst);
  1480. +
  1481. + platform_set_drvdata(pdev, inst);
  1482. +
  1483. + dev_info(inst->dev, "initialised");
  1484. +
  1485. + return 0;
  1486. +}
  1487. +
  1488. +/****************************************************************************
  1489. +*
  1490. +* bcm2835_smi_remove - called when the driver is unloaded.
  1491. +*
  1492. +***************************************************************************/
  1493. +
  1494. +static int bcm2835_smi_remove(struct platform_device *pdev)
  1495. +{
  1496. + struct bcm2835_smi_instance *inst = platform_get_drvdata(pdev);
  1497. + struct device *dev = inst->dev;
  1498. +
  1499. + dev_info(dev, "SMI device removed - OK");
  1500. + return 0;
  1501. +}
  1502. +
  1503. +/****************************************************************************
  1504. +*
  1505. +* Register the driver with device tree
  1506. +*
  1507. +***************************************************************************/
  1508. +
  1509. +static const struct of_device_id bcm2835_smi_of_match[] = {
  1510. + {.compatible = "brcm,bcm2835-smi",},
  1511. + { /* sentinel */ },
  1512. +};
  1513. +
  1514. +MODULE_DEVICE_TABLE(of, bcm2835_smi_of_match);
  1515. +
  1516. +static struct platform_driver bcm2835_smi_driver = {
  1517. + .probe = bcm2835_smi_probe,
  1518. + .remove = bcm2835_smi_remove,
  1519. + .driver = {
  1520. + .name = DRIVER_NAME,
  1521. + .owner = THIS_MODULE,
  1522. + .of_match_table = bcm2835_smi_of_match,
  1523. + },
  1524. +};
  1525. +
  1526. +module_platform_driver(bcm2835_smi_driver);
  1527. +
  1528. +MODULE_ALIAS("platform:smi-bcm2835");
  1529. +MODULE_LICENSE("GPL");
  1530. +MODULE_DESCRIPTION("Device driver for BCM2835's secondary memory interface");
  1531. +MODULE_AUTHOR("Luke Wren <luke@raspberrypi.org>");
  1532. --- /dev/null
  1533. +++ b/include/linux/broadcom/bcm2835_smi.h
  1534. @@ -0,0 +1,391 @@
  1535. +/**
  1536. + * Declarations and definitions for Broadcom's Secondary Memory Interface
  1537. + *
  1538. + * Written by Luke Wren <luke@raspberrypi.org>
  1539. + * Copyright (c) 2015, Raspberry Pi (Trading) Ltd.
  1540. + * Copyright (c) 2010-2012 Broadcom. All rights reserved.
  1541. + *
  1542. + * Redistribution and use in source and binary forms, with or without
  1543. + * modification, are permitted provided that the following conditions
  1544. + * are met:
  1545. + * 1. Redistributions of source code must retain the above copyright
  1546. + * notice, this list of conditions, and the following disclaimer,
  1547. + * without modification.
  1548. + * 2. Redistributions in binary form must reproduce the above copyright
  1549. + * notice, this list of conditions and the following disclaimer in the
  1550. + * documentation and/or other materials provided with the distribution.
  1551. + * 3. The names of the above-listed copyright holders may not be used
  1552. + * to endorse or promote products derived from this software without
  1553. + * specific prior written permission.
  1554. + *
  1555. + * ALTERNATIVELY, this software may be distributed under the terms of the
  1556. + * GNU General Public License ("GPL") version 2, as published by the Free
  1557. + * Software Foundation.
  1558. + *
  1559. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  1560. + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  1561. + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  1562. + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  1563. + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  1564. + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  1565. + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  1566. + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  1567. + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  1568. + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  1569. + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  1570. + */
  1571. +
  1572. +#ifndef BCM2835_SMI_H
  1573. +#define BCM2835_SMI_H
  1574. +
  1575. +#include <linux/ioctl.h>
  1576. +
  1577. +#ifndef __KERNEL__
  1578. +#include <stdint.h>
  1579. +#include <stdbool.h>
  1580. +#endif
  1581. +
  1582. +#define BCM2835_SMI_IOC_MAGIC 0x1
  1583. +#define BCM2835_SMI_INVALID_HANDLE (~0)
  1584. +
  1585. +/* IOCTLs 0x100...0x1ff are not device-specific - we can use them */
  1586. +#define BCM2835_SMI_IOC_GET_SETTINGS _IO(BCM2835_SMI_IOC_MAGIC, 0)
  1587. +#define BCM2835_SMI_IOC_WRITE_SETTINGS _IO(BCM2835_SMI_IOC_MAGIC, 1)
  1588. +#define BCM2835_SMI_IOC_ADDRESS _IO(BCM2835_SMI_IOC_MAGIC, 2)
  1589. +#define BCM2835_SMI_IOC_MAX 2
  1590. +
  1591. +#define SMI_WIDTH_8BIT 0
  1592. +#define SMI_WIDTH_16BIT 1
  1593. +#define SMI_WIDTH_9BIT 2
  1594. +#define SMI_WIDTH_18BIT 3
  1595. +
  1596. +/* max number of bytes where DMA will not be used */
  1597. +#define DMA_THRESHOLD_BYTES 128
  1598. +#define DMA_BOUNCE_BUFFER_SIZE (1024 * 1024 / 2)
  1599. +#define DMA_BOUNCE_BUFFER_COUNT 3
  1600. +
  1601. +
  1602. +struct smi_settings {
  1603. + int data_width;
  1604. + /* Whether or not to pack multiple SMI transfers into a
  1605. + single 32 bit FIFO word */
  1606. + bool pack_data;
  1607. +
  1608. + /* Timing for reads (writes the same but for WE)
  1609. + *
  1610. + * OE ----------+ +--------------------
  1611. + * | |
  1612. + * +----------+
  1613. + * SD -<==============================>-----------
  1614. + * SA -<=========================================>-
  1615. + * <-setup-> <-strobe -> <-hold -> <- pace ->
  1616. + */
  1617. +
  1618. + int read_setup_time;
  1619. + int read_hold_time;
  1620. + int read_pace_time;
  1621. + int read_strobe_time;
  1622. +
  1623. + int write_setup_time;
  1624. + int write_hold_time;
  1625. + int write_pace_time;
  1626. + int write_strobe_time;
  1627. +
  1628. + bool dma_enable; /* DREQs */
  1629. + bool dma_passthrough_enable; /* External DREQs */
  1630. + int dma_read_thresh;
  1631. + int dma_write_thresh;
  1632. + int dma_panic_read_thresh;
  1633. + int dma_panic_write_thresh;
  1634. +};
  1635. +
  1636. +/****************************************************************************
  1637. +*
  1638. +* Declare exported SMI functions
  1639. +*
  1640. +***************************************************************************/
  1641. +
  1642. +#ifdef __KERNEL__
  1643. +
  1644. +#include <linux/dmaengine.h> /* for enum dma_transfer_direction */
  1645. +#include <linux/of.h>
  1646. +#include <linux/semaphore.h>
  1647. +
  1648. +struct bcm2835_smi_instance;
  1649. +
  1650. +struct bcm2835_smi_bounce_info {
  1651. + struct semaphore callback_sem;
  1652. + void *buffer[DMA_BOUNCE_BUFFER_COUNT];
  1653. + dma_addr_t phys[DMA_BOUNCE_BUFFER_COUNT];
  1654. + struct scatterlist sgl[DMA_BOUNCE_BUFFER_COUNT];
  1655. +};
  1656. +
  1657. +
  1658. +void bcm2835_smi_set_regs_from_settings(struct bcm2835_smi_instance *);
  1659. +
  1660. +struct smi_settings *bcm2835_smi_get_settings_from_regs(
  1661. + struct bcm2835_smi_instance *inst);
  1662. +
  1663. +void bcm2835_smi_write_buf(
  1664. + struct bcm2835_smi_instance *inst,
  1665. + const void *buf,
  1666. + size_t n_bytes);
  1667. +
  1668. +void bcm2835_smi_read_buf(
  1669. + struct bcm2835_smi_instance *inst,
  1670. + void *buf,
  1671. + size_t n_bytes);
  1672. +
  1673. +void bcm2835_smi_set_address(struct bcm2835_smi_instance *inst,
  1674. + unsigned int address);
  1675. +
  1676. +ssize_t bcm2835_smi_user_dma(
  1677. + struct bcm2835_smi_instance *inst,
  1678. + enum dma_transfer_direction dma_dir,
  1679. + char __user *user_ptr,
  1680. + size_t count,
  1681. + struct bcm2835_smi_bounce_info **bounce);
  1682. +
  1683. +struct bcm2835_smi_instance *bcm2835_smi_get(struct device_node *node);
  1684. +
  1685. +#endif /* __KERNEL__ */
  1686. +
  1687. +/****************************************************************
  1688. +*
  1689. +* Implementation-only declarations
  1690. +*
  1691. +****************************************************************/
  1692. +
  1693. +#ifdef BCM2835_SMI_IMPLEMENTATION
  1694. +
  1695. +/* Clock manager registers for SMI clock: */
  1696. +#define CM_SMI_BASE_ADDRESS ((BCM2708_PERI_BASE) + 0x1010b0)
  1697. +/* Clock manager "password" to protect registers from spurious writes */
  1698. +#define CM_PWD (0x5a << 24)
  1699. +
  1700. +#define CM_SMI_CTL 0x00
  1701. +#define CM_SMI_DIV 0x04
  1702. +
  1703. +#define CM_SMI_CTL_FLIP (1 << 8)
  1704. +#define CM_SMI_CTL_BUSY (1 << 7)
  1705. +#define CM_SMI_CTL_KILL (1 << 5)
  1706. +#define CM_SMI_CTL_ENAB (1 << 4)
  1707. +#define CM_SMI_CTL_SRC_MASK (0xf)
  1708. +#define CM_SMI_CTL_SRC_OFFS (0)
  1709. +
  1710. +#define CM_SMI_DIV_DIVI_MASK (0xf << 12)
  1711. +#define CM_SMI_DIV_DIVI_OFFS (12)
  1712. +#define CM_SMI_DIV_DIVF_MASK (0xff << 4)
  1713. +#define CM_SMI_DIV_DIVF_OFFS (4)
  1714. +
  1715. +/* SMI register mapping:*/
  1716. +#define SMI_BASE_ADDRESS ((BCM2708_PERI_BASE) + 0x600000)
  1717. +
  1718. +#define SMICS 0x00 /* control + status register */
  1719. +#define SMIL 0x04 /* length/count (n external txfers) */
  1720. +#define SMIA 0x08 /* address register */
  1721. +#define SMID 0x0c /* data register */
  1722. +#define SMIDSR0 0x10 /* device 0 read settings */
  1723. +#define SMIDSW0 0x14 /* device 0 write settings */
  1724. +#define SMIDSR1 0x18 /* device 1 read settings */
  1725. +#define SMIDSW1 0x1c /* device 1 write settings */
  1726. +#define SMIDSR2 0x20 /* device 2 read settings */
  1727. +#define SMIDSW2 0x24 /* device 2 write settings */
  1728. +#define SMIDSR3 0x28 /* device 3 read settings */
  1729. +#define SMIDSW3 0x2c /* device 3 write settings */
  1730. +#define SMIDC 0x30 /* DMA control registers */
  1731. +#define SMIDCS 0x34 /* direct control/status register */
  1732. +#define SMIDA 0x38 /* direct address register */
  1733. +#define SMIDD 0x3c /* direct data registers */
  1734. +#define SMIFD 0x40 /* FIFO debug register */
  1735. +
  1736. +
  1737. +
  1738. +/* Control and Status register bits:
  1739. + * SMICS_RXF : RX fifo full: 1 when RX fifo is full
  1740. + * SMICS_TXE : TX fifo empty: 1 when empty.
  1741. + * SMICS_RXD : RX fifo contains data: 1 when there is data.
  1742. + * SMICS_TXD : TX fifo can accept data: 1 when true.
  1743. + * SMICS_RXR : RX fifo needs reading: 1 when fifo more than 3/4 full, or
  1744. + * when "DONE" and fifo not emptied.
  1745. + * SMICS_TXW : TX fifo needs writing: 1 when less than 1/4 full.
  1746. + * SMICS_AFERR : AXI FIFO error: 1 when fifo read when empty or written
  1747. + * when full. Write 1 to clear.
  1748. + * SMICS_EDREQ : 1 when external DREQ received.
  1749. + * SMICS_PXLDAT : Pixel data: write 1 to enable pixel transfer modes.
  1750. + * SMICS_SETERR : 1 if there was an error writing to setup regs (e.g.
  1751. + * tx was in progress). Write 1 to clear.
  1752. + * SMICS_PVMODE : Set to 1 to enable pixel valve mode.
  1753. + * SMICS_INTR : Set to 1 to enable interrupt on RX.
  1754. + * SMICS_INTT : Set to 1 to enable interrupt on TX.
  1755. + * SMICS_INTD : Set to 1 to enable interrupt on DONE condition.
  1756. + * SMICS_TEEN : Tear effect mode enabled: Programmed transfers will wait
  1757. + * for a TE trigger before writing.
  1758. + * SMICS_PAD1 : Padding settings for external transfers. For writes: the
  1759. + * number of bytes initially written to the TX fifo that
  1760. + * SMICS_PAD0 : should be ignored. For reads: the number of bytes that will
  1761. + * be read before the data, and should be dropped.
  1762. + * SMICS_WRITE : Transfer direction: 1 = write to external device, 0 = read
  1763. + * SMICS_CLEAR : Write 1 to clear the FIFOs.
  1764. + * SMICS_START : Write 1 to start the programmed transfer.
  1765. + * SMICS_ACTIVE : Reads as 1 when a programmed transfer is underway.
  1766. + * SMICS_DONE : Reads as 1 when transfer finished. For RX, not set until
  1767. + * FIFO emptied.
  1768. + * SMICS_ENABLE : Set to 1 to enable the SMI peripheral, 0 to disable.
  1769. + */
  1770. +
  1771. +#define SMICS_RXF (1 << 31)
  1772. +#define SMICS_TXE (1 << 30)
  1773. +#define SMICS_RXD (1 << 29)
  1774. +#define SMICS_TXD (1 << 28)
  1775. +#define SMICS_RXR (1 << 27)
  1776. +#define SMICS_TXW (1 << 26)
  1777. +#define SMICS_AFERR (1 << 25)
  1778. +#define SMICS_EDREQ (1 << 15)
  1779. +#define SMICS_PXLDAT (1 << 14)
  1780. +#define SMICS_SETERR (1 << 13)
  1781. +#define SMICS_PVMODE (1 << 12)
  1782. +#define SMICS_INTR (1 << 11)
  1783. +#define SMICS_INTT (1 << 10)
  1784. +#define SMICS_INTD (1 << 9)
  1785. +#define SMICS_TEEN (1 << 8)
  1786. +#define SMICS_PAD1 (1 << 7)
  1787. +#define SMICS_PAD0 (1 << 6)
  1788. +#define SMICS_WRITE (1 << 5)
  1789. +#define SMICS_CLEAR (1 << 4)
  1790. +#define SMICS_START (1 << 3)
  1791. +#define SMICS_ACTIVE (1 << 2)
  1792. +#define SMICS_DONE (1 << 1)
  1793. +#define SMICS_ENABLE (1 << 0)
  1794. +
  1795. +/* Address register bits: */
  1796. +
  1797. +#define SMIA_DEVICE_MASK ((1 << 9) | (1 << 8))
  1798. +#define SMIA_DEVICE_OFFS (8)
  1799. +#define SMIA_ADDR_MASK (0x3f) /* bits 5 -> 0 */
  1800. +#define SMIA_ADDR_OFFS (0)
  1801. +
  1802. +/* DMA control register bits:
  1803. + * SMIDC_DMAEN : DMA enable: set 1: DMA requests will be issued.
  1804. + * SMIDC_DMAP : DMA passthrough: when set to 0, top two data pins are used by
  1805. + * SMI as usual. When set to 1, the top two pins are used for
  1806. + * external DREQs: pin 16 read request, 17 write.
  1807. + * SMIDC_PANIC* : Threshold at which DMA will panic during read/write.
  1808. + * SMIDC_REQ* : Threshold at which DMA will generate a DREQ.
  1809. + */
  1810. +
  1811. +#define SMIDC_DMAEN (1 << 28)
  1812. +#define SMIDC_DMAP (1 << 24)
  1813. +#define SMIDC_PANICR_MASK (0x3f << 18)
  1814. +#define SMIDC_PANICR_OFFS (18)
  1815. +#define SMIDC_PANICW_MASK (0x3f << 12)
  1816. +#define SMIDC_PANICW_OFFS (12)
  1817. +#define SMIDC_REQR_MASK (0x3f << 6)
  1818. +#define SMIDC_REQR_OFFS (6)
  1819. +#define SMIDC_REQW_MASK (0x3f)
  1820. +#define SMIDC_REQW_OFFS (0)
  1821. +
  1822. +/* Device settings register bits: same for all 4 (or 3?) device register sets.
  1823. + * Device read settings:
  1824. + * SMIDSR_RWIDTH : Read transfer width. 00 = 8bit, 01 = 16bit,
  1825. + * 10 = 18bit, 11 = 9bit.
  1826. + * SMIDSR_RSETUP : Read setup time: number of core cycles between chip
  1827. + * select/address and read strobe. Min 1, max 64.
  1828. + * SMIDSR_MODE68 : 1 for System 68 mode (i.e. enable + direction pins,
  1829. + * rather than OE + WE pin)
  1830. + * SMIDSR_FSETUP : If set to 1, setup time only applies to first
  1831. + * transfer after address change.
  1832. + * SMIDSR_RHOLD : Number of core cycles between read strobe going
  1833. + * inactive and CS/address going inactive. Min 1, max 64
  1834. + * SMIDSR_RPACEALL : When set to 1, this device's RPACE value will always
  1835. + * be used for the next transaction, even if it is not
  1836. + * to this device.
  1837. + * SMIDSR_RPACE : Number of core cycles spent waiting between CS
  1838. + * deassert and start of next transfer. Min 1, max 128
  1839. + * SMIDSR_RDREQ : 1 = use external DMA request on SD16 to pace reads
  1840. + * from device. Must also set DMAP in SMICS.
  1841. + * SMIDSR_RSTROBE : Number of cycles to assert the read strobe.
  1842. + * min 1, max 128.
  1843. + */
  1844. +#define SMIDSR_RWIDTH_MASK ((1<<31)|(1<<30))
  1845. +#define SMIDSR_RWIDTH_OFFS (30)
  1846. +#define SMIDSR_RSETUP_MASK (0x3f << 24)
  1847. +#define SMIDSR_RSETUP_OFFS (24)
  1848. +#define SMIDSR_MODE68 (1 << 23)
  1849. +#define SMIDSR_FSETUP (1 << 22)
  1850. +#define SMIDSR_RHOLD_MASK (0x3f << 16)
  1851. +#define SMIDSR_RHOLD_OFFS (16)
  1852. +#define SMIDSR_RPACEALL (1 << 15)
  1853. +#define SMIDSR_RPACE_MASK (0x7f << 8)
  1854. +#define SMIDSR_RPACE_OFFS (8)
  1855. +#define SMIDSR_RDREQ (1 << 7)
  1856. +#define SMIDSR_RSTROBE_MASK (0x7f)
  1857. +#define SMIDSR_RSTROBE_OFFS (0)
  1858. +
  1859. +/* Device write settings:
  1860. + * SMIDSW_WWIDTH : Write transfer width. 00 = 8bit, 01 = 16bit,
  1861. + * 10= 18bit, 11 = 9bit.
  1862. + * SMIDSW_WSETUP : Number of cycles between CS assert and write strobe.
  1863. + * Min 1, max 64.
  1864. + * SMIDSW_WFORMAT : Pixel format of input. 0 = 16bit RGB 565,
  1865. + * 1 = 32bit RGBA 8888
  1866. + * SMIDSW_WSWAP : 1 = swap pixel data bits. (Use with SMICS_PXLDAT)
  1867. + * SMIDSW_WHOLD : Time between WE deassert and CS deassert. 1 to 64
  1868. + * SMIDSW_WPACEALL : 1: this device's WPACE will be used for the next
  1869. + * transfer, regardless of that transfer's device.
  1870. + * SMIDSW_WPACE : Cycles between CS deassert and next CS assert.
  1871. + * Min 1, max 128
  1872. + * SMIDSW_WDREQ : Use external DREQ on pin 17 to pace writes. DMAP must
  1873. + * be set in SMICS.
  1874. + * SMIDSW_WSTROBE : Number of cycles to assert the write strobe.
  1875. + * Min 1, max 128
  1876. + */
  1877. +#define SMIDSW_WWIDTH_MASK ((1<<31)|(1<<30))
  1878. +#define SMIDSW_WWIDTH_OFFS (30)
  1879. +#define SMIDSW_WSETUP_MASK (0x3f << 24)
  1880. +#define SMIDSW_WSETUP_OFFS (24)
  1881. +#define SMIDSW_WFORMAT (1 << 23)
  1882. +#define SMIDSW_WSWAP (1 << 22)
  1883. +#define SMIDSW_WHOLD_MASK (0x3f << 16)
  1884. +#define SMIDSW_WHOLD_OFFS (16)
  1885. +#define SMIDSW_WPACEALL (1 << 15)
  1886. +#define SMIDSW_WPACE_MASK (0x7f << 8)
  1887. +#define SMIDSW_WPACE_OFFS (8)
  1888. +#define SMIDSW_WDREQ (1 << 7)
  1889. +#define SMIDSW_WSTROBE_MASK (0x7f)
  1890. +#define SMIDSW_WSTROBE_OFFS (0)
  1891. +
  1892. +/* Direct transfer control + status register
  1893. + * SMIDCS_WRITE : Direction of transfer: 1 -> write, 0 -> read
  1894. + * SMIDCS_DONE : 1 when a transfer has finished. Write 1 to clear.
  1895. + * SMIDCS_START : Write 1 to start a transfer, if one is not already underway.
  1896. + * SMIDCE_ENABLE: Write 1 to enable SMI in direct mode.
  1897. + */
  1898. +
  1899. +#define SMIDCS_WRITE (1 << 3)
  1900. +#define SMIDCS_DONE (1 << 2)
  1901. +#define SMIDCS_START (1 << 1)
  1902. +#define SMIDCS_ENABLE (1 << 0)
  1903. +
  1904. +/* Direct transfer address register
  1905. + * SMIDA_DEVICE : Indicates which of the device settings banks should be used.
  1906. + * SMIDA_ADDR : The value to be asserted on the address pins.
  1907. + */
  1908. +
  1909. +#define SMIDA_DEVICE_MASK ((1<<9)|(1<<8))
  1910. +#define SMIDA_DEVICE_OFFS (8)
  1911. +#define SMIDA_ADDR_MASK (0x3f)
  1912. +#define SMIDA_ADDR_OFFS (0)
  1913. +
  1914. +/* FIFO debug register
  1915. + * SMIFD_FLVL : The high-tide mark of FIFO count during the most recent txfer
  1916. + * SMIFD_FCNT : The current FIFO count.
  1917. + */
  1918. +#define SMIFD_FLVL_MASK (0x3f << 8)
  1919. +#define SMIFD_FLVL_OFFS (8)
  1920. +#define SMIFD_FCNT_MASK (0x3f)
  1921. +#define SMIFD_FCNT_OFFS (0)
  1922. +
  1923. +#endif /* BCM2835_SMI_IMPLEMENTATION */
  1924. +
  1925. +#endif /* BCM2835_SMI_H */