0260-clk-bcm2835-reorganize-bcm2835_clock_array-assignmen.patch 26 KB

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  1. From 9d38f8ad8156a83b2f9e3c68ddf87541a8511395 Mon Sep 17 00:00:00 2001
  2. From: Martin Sperl <kernel@martin.sperl.org>
  3. Date: Mon, 29 Feb 2016 12:51:42 +0000
  4. Subject: [PATCH] clk: bcm2835: reorganize bcm2835_clock_array assignment
  5. Reorganize bcm2835_clock_array so that there is no more
  6. need for separate bcm2835_*_data structures to be defined.
  7. Instead the required structures are generated inline via
  8. helper macros.
  9. To allow this to also work for pll alone it was required that
  10. the parent_pll was changed from a pointer to bcm2835_pll_data
  11. to the name of the pll instead.
  12. Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
  13. Signed-off-by: Eric Anholt <eric@anholt.net>
  14. Reviewed-by: Eric Anholt <eric@anholt.net>
  15. (cherry picked from commit 3b15afefbef9b5952e3d68ad73d93f981b9faca8)
  16. ---
  17. drivers/clk/bcm/clk-bcm2835.c | 852 +++++++++++++++++++-----------------------
  18. 1 file changed, 393 insertions(+), 459 deletions(-)
  19. --- a/drivers/clk/bcm/clk-bcm2835.c
  20. +++ b/drivers/clk/bcm/clk-bcm2835.c
  21. @@ -418,115 +418,10 @@ static const struct bcm2835_pll_ana_bits
  22. .fb_prediv_mask = BIT(11),
  23. };
  24. -/*
  25. - * PLLA is the auxiliary PLL, used to drive the CCP2 (Compact Camera
  26. - * Port 2) transmitter clock.
  27. - *
  28. - * It is in the PX LDO power domain, which is on when the AUDIO domain
  29. - * is on.
  30. - */
  31. -static const struct bcm2835_pll_data bcm2835_plla_data = {
  32. - .name = "plla",
  33. - .cm_ctrl_reg = CM_PLLA,
  34. - .a2w_ctrl_reg = A2W_PLLA_CTRL,
  35. - .frac_reg = A2W_PLLA_FRAC,
  36. - .ana_reg_base = A2W_PLLA_ANA0,
  37. - .reference_enable_mask = A2W_XOSC_CTRL_PLLA_ENABLE,
  38. - .lock_mask = CM_LOCK_FLOCKA,
  39. -
  40. - .ana = &bcm2835_ana_default,
  41. -
  42. - .min_rate = 600000000u,
  43. - .max_rate = 2400000000u,
  44. - .max_fb_rate = BCM2835_MAX_FB_RATE,
  45. -};
  46. -
  47. -/* PLLB is used for the ARM's clock. */
  48. -static const struct bcm2835_pll_data bcm2835_pllb_data = {
  49. - .name = "pllb",
  50. - .cm_ctrl_reg = CM_PLLB,
  51. - .a2w_ctrl_reg = A2W_PLLB_CTRL,
  52. - .frac_reg = A2W_PLLB_FRAC,
  53. - .ana_reg_base = A2W_PLLB_ANA0,
  54. - .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE,
  55. - .lock_mask = CM_LOCK_FLOCKB,
  56. -
  57. - .ana = &bcm2835_ana_default,
  58. -
  59. - .min_rate = 600000000u,
  60. - .max_rate = 3000000000u,
  61. - .max_fb_rate = BCM2835_MAX_FB_RATE,
  62. -};
  63. -
  64. -/*
  65. - * PLLC is the core PLL, used to drive the core VPU clock.
  66. - *
  67. - * It is in the PX LDO power domain, which is on when the AUDIO domain
  68. - * is on.
  69. -*/
  70. -static const struct bcm2835_pll_data bcm2835_pllc_data = {
  71. - .name = "pllc",
  72. - .cm_ctrl_reg = CM_PLLC,
  73. - .a2w_ctrl_reg = A2W_PLLC_CTRL,
  74. - .frac_reg = A2W_PLLC_FRAC,
  75. - .ana_reg_base = A2W_PLLC_ANA0,
  76. - .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
  77. - .lock_mask = CM_LOCK_FLOCKC,
  78. -
  79. - .ana = &bcm2835_ana_default,
  80. -
  81. - .min_rate = 600000000u,
  82. - .max_rate = 3000000000u,
  83. - .max_fb_rate = BCM2835_MAX_FB_RATE,
  84. -};
  85. -
  86. -/*
  87. - * PLLD is the display PLL, used to drive DSI display panels.
  88. - *
  89. - * It is in the PX LDO power domain, which is on when the AUDIO domain
  90. - * is on.
  91. - */
  92. -static const struct bcm2835_pll_data bcm2835_plld_data = {
  93. - .name = "plld",
  94. - .cm_ctrl_reg = CM_PLLD,
  95. - .a2w_ctrl_reg = A2W_PLLD_CTRL,
  96. - .frac_reg = A2W_PLLD_FRAC,
  97. - .ana_reg_base = A2W_PLLD_ANA0,
  98. - .reference_enable_mask = A2W_XOSC_CTRL_DDR_ENABLE,
  99. - .lock_mask = CM_LOCK_FLOCKD,
  100. -
  101. - .ana = &bcm2835_ana_default,
  102. -
  103. - .min_rate = 600000000u,
  104. - .max_rate = 2400000000u,
  105. - .max_fb_rate = BCM2835_MAX_FB_RATE,
  106. -};
  107. -
  108. -/*
  109. - * PLLH is used to supply the pixel clock or the AUX clock for the TV
  110. - * encoder.
  111. - *
  112. - * It is in the HDMI power domain.
  113. - */
  114. -static const struct bcm2835_pll_data bcm2835_pllh_data = {
  115. - "pllh",
  116. - .cm_ctrl_reg = CM_PLLH,
  117. - .a2w_ctrl_reg = A2W_PLLH_CTRL,
  118. - .frac_reg = A2W_PLLH_FRAC,
  119. - .ana_reg_base = A2W_PLLH_ANA0,
  120. - .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
  121. - .lock_mask = CM_LOCK_FLOCKH,
  122. -
  123. - .ana = &bcm2835_ana_pllh,
  124. -
  125. - .min_rate = 600000000u,
  126. - .max_rate = 3000000000u,
  127. - .max_fb_rate = BCM2835_MAX_FB_RATE,
  128. -};
  129. -
  130. struct bcm2835_pll_divider_data {
  131. const char *name;
  132. - const struct bcm2835_pll_data *source_pll;
  133. + const char *source_pll;
  134. +
  135. u32 cm_reg;
  136. u32 a2w_reg;
  137. @@ -535,124 +430,6 @@ struct bcm2835_pll_divider_data {
  138. u32 fixed_divider;
  139. };
  140. -static const struct bcm2835_pll_divider_data bcm2835_plla_core_data = {
  141. - .name = "plla_core",
  142. - .source_pll = &bcm2835_plla_data,
  143. - .cm_reg = CM_PLLA,
  144. - .a2w_reg = A2W_PLLA_CORE,
  145. - .load_mask = CM_PLLA_LOADCORE,
  146. - .hold_mask = CM_PLLA_HOLDCORE,
  147. - .fixed_divider = 1,
  148. -};
  149. -
  150. -static const struct bcm2835_pll_divider_data bcm2835_plla_per_data = {
  151. - .name = "plla_per",
  152. - .source_pll = &bcm2835_plla_data,
  153. - .cm_reg = CM_PLLA,
  154. - .a2w_reg = A2W_PLLA_PER,
  155. - .load_mask = CM_PLLA_LOADPER,
  156. - .hold_mask = CM_PLLA_HOLDPER,
  157. - .fixed_divider = 1,
  158. -};
  159. -
  160. -static const struct bcm2835_pll_divider_data bcm2835_pllb_arm_data = {
  161. - .name = "pllb_arm",
  162. - .source_pll = &bcm2835_pllb_data,
  163. - .cm_reg = CM_PLLB,
  164. - .a2w_reg = A2W_PLLB_ARM,
  165. - .load_mask = CM_PLLB_LOADARM,
  166. - .hold_mask = CM_PLLB_HOLDARM,
  167. - .fixed_divider = 1,
  168. -};
  169. -
  170. -static const struct bcm2835_pll_divider_data bcm2835_pllc_core0_data = {
  171. - .name = "pllc_core0",
  172. - .source_pll = &bcm2835_pllc_data,
  173. - .cm_reg = CM_PLLC,
  174. - .a2w_reg = A2W_PLLC_CORE0,
  175. - .load_mask = CM_PLLC_LOADCORE0,
  176. - .hold_mask = CM_PLLC_HOLDCORE0,
  177. - .fixed_divider = 1,
  178. -};
  179. -
  180. -static const struct bcm2835_pll_divider_data bcm2835_pllc_core1_data = {
  181. - .name = "pllc_core1", .source_pll = &bcm2835_pllc_data,
  182. - .cm_reg = CM_PLLC, A2W_PLLC_CORE1,
  183. - .load_mask = CM_PLLC_LOADCORE1,
  184. - .hold_mask = CM_PLLC_HOLDCORE1,
  185. - .fixed_divider = 1,
  186. -};
  187. -
  188. -static const struct bcm2835_pll_divider_data bcm2835_pllc_core2_data = {
  189. - .name = "pllc_core2",
  190. - .source_pll = &bcm2835_pllc_data,
  191. - .cm_reg = CM_PLLC,
  192. - .a2w_reg = A2W_PLLC_CORE2,
  193. - .load_mask = CM_PLLC_LOADCORE2,
  194. - .hold_mask = CM_PLLC_HOLDCORE2,
  195. - .fixed_divider = 1,
  196. -};
  197. -
  198. -static const struct bcm2835_pll_divider_data bcm2835_pllc_per_data = {
  199. - .name = "pllc_per",
  200. - .source_pll = &bcm2835_pllc_data,
  201. - .cm_reg = CM_PLLC,
  202. - .a2w_reg = A2W_PLLC_PER,
  203. - .load_mask = CM_PLLC_LOADPER,
  204. - .hold_mask = CM_PLLC_HOLDPER,
  205. - .fixed_divider = 1,
  206. -};
  207. -
  208. -static const struct bcm2835_pll_divider_data bcm2835_plld_core_data = {
  209. - .name = "plld_core",
  210. - .source_pll = &bcm2835_plld_data,
  211. - .cm_reg = CM_PLLD,
  212. - .a2w_reg = A2W_PLLD_CORE,
  213. - .load_mask = CM_PLLD_LOADCORE,
  214. - .hold_mask = CM_PLLD_HOLDCORE,
  215. - .fixed_divider = 1,
  216. -};
  217. -
  218. -static const struct bcm2835_pll_divider_data bcm2835_plld_per_data = {
  219. - .name = "plld_per",
  220. - .source_pll = &bcm2835_plld_data,
  221. - .cm_reg = CM_PLLD,
  222. - .a2w_reg = A2W_PLLD_PER,
  223. - .load_mask = CM_PLLD_LOADPER,
  224. - .hold_mask = CM_PLLD_HOLDPER,
  225. - .fixed_divider = 1,
  226. -};
  227. -
  228. -static const struct bcm2835_pll_divider_data bcm2835_pllh_rcal_data = {
  229. - .name = "pllh_rcal",
  230. - .source_pll = &bcm2835_pllh_data,
  231. - .cm_reg = CM_PLLH,
  232. - .a2w_reg = A2W_PLLH_RCAL,
  233. - .load_mask = CM_PLLH_LOADRCAL,
  234. - .hold_mask = 0,
  235. - .fixed_divider = 10,
  236. -};
  237. -
  238. -static const struct bcm2835_pll_divider_data bcm2835_pllh_aux_data = {
  239. - .name = "pllh_aux",
  240. - .source_pll = &bcm2835_pllh_data,
  241. - .cm_reg = CM_PLLH,
  242. - .a2w_reg = A2W_PLLH_AUX,
  243. - .load_mask = CM_PLLH_LOADAUX,
  244. - .hold_mask = 0,
  245. - .fixed_divider = 10,
  246. -};
  247. -
  248. -static const struct bcm2835_pll_divider_data bcm2835_pllh_pix_data = {
  249. - .name = "pllh_pix",
  250. - .source_pll = &bcm2835_pllh_data,
  251. - .cm_reg = CM_PLLH,
  252. - .a2w_reg = A2W_PLLH_PIX,
  253. - .load_mask = CM_PLLH_LOADPIX,
  254. - .hold_mask = 0,
  255. - .fixed_divider = 10,
  256. -};
  257. -
  258. struct bcm2835_clock_data {
  259. const char *name;
  260. @@ -671,188 +448,6 @@ struct bcm2835_clock_data {
  261. bool is_mash_clock;
  262. };
  263. -static const char *const bcm2835_clock_per_parents[] = {
  264. - "gnd",
  265. - "xosc",
  266. - "testdebug0",
  267. - "testdebug1",
  268. - "plla_per",
  269. - "pllc_per",
  270. - "plld_per",
  271. - "pllh_aux",
  272. -};
  273. -
  274. -static const char *const bcm2835_clock_vpu_parents[] = {
  275. - "gnd",
  276. - "xosc",
  277. - "testdebug0",
  278. - "testdebug1",
  279. - "plla_core",
  280. - "pllc_core0",
  281. - "plld_core",
  282. - "pllh_aux",
  283. - "pllc_core1",
  284. - "pllc_core2",
  285. -};
  286. -
  287. -static const char *const bcm2835_clock_osc_parents[] = {
  288. - "gnd",
  289. - "xosc",
  290. - "testdebug0",
  291. - "testdebug1"
  292. -};
  293. -
  294. -/*
  295. - * Used for a 1Mhz clock for the system clocksource, and also used by
  296. - * the watchdog timer and the camera pulse generator.
  297. - */
  298. -static const struct bcm2835_clock_data bcm2835_clock_timer_data = {
  299. - .name = "timer",
  300. - .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents),
  301. - .parents = bcm2835_clock_osc_parents,
  302. - .ctl_reg = CM_TIMERCTL,
  303. - .div_reg = CM_TIMERDIV,
  304. - .int_bits = 6,
  305. - .frac_bits = 12,
  306. -};
  307. -
  308. -/* One Time Programmable Memory clock. Maximum 10Mhz. */
  309. -static const struct bcm2835_clock_data bcm2835_clock_otp_data = {
  310. - .name = "otp",
  311. - .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents),
  312. - .parents = bcm2835_clock_osc_parents,
  313. - .ctl_reg = CM_OTPCTL,
  314. - .div_reg = CM_OTPDIV,
  315. - .int_bits = 4,
  316. - .frac_bits = 0,
  317. -};
  318. -
  319. -/*
  320. - * VPU clock. This doesn't have an enable bit, since it drives the
  321. - * bus for everything else, and is special so it doesn't need to be
  322. - * gated for rate changes. It is also known as "clk_audio" in various
  323. - * hardware documentation.
  324. - */
  325. -static const struct bcm2835_clock_data bcm2835_clock_vpu_data = {
  326. - .name = "vpu",
  327. - .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),
  328. - .parents = bcm2835_clock_vpu_parents,
  329. - .ctl_reg = CM_VPUCTL,
  330. - .div_reg = CM_VPUDIV,
  331. - .int_bits = 12,
  332. - .frac_bits = 8,
  333. - .is_vpu_clock = true,
  334. -};
  335. -
  336. -static const struct bcm2835_clock_data bcm2835_clock_v3d_data = {
  337. - .name = "v3d",
  338. - .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),
  339. - .parents = bcm2835_clock_vpu_parents,
  340. - .ctl_reg = CM_V3DCTL,
  341. - .div_reg = CM_V3DDIV,
  342. - .int_bits = 4,
  343. - .frac_bits = 8,
  344. -};
  345. -
  346. -static const struct bcm2835_clock_data bcm2835_clock_isp_data = {
  347. - .name = "isp",
  348. - .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),
  349. - .parents = bcm2835_clock_vpu_parents,
  350. - .ctl_reg = CM_ISPCTL,
  351. - .div_reg = CM_ISPDIV,
  352. - .int_bits = 4,
  353. - .frac_bits = 8,
  354. -};
  355. -
  356. -static const struct bcm2835_clock_data bcm2835_clock_h264_data = {
  357. - .name = "h264",
  358. - .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),
  359. - .parents = bcm2835_clock_vpu_parents,
  360. - .ctl_reg = CM_H264CTL,
  361. - .div_reg = CM_H264DIV,
  362. - .int_bits = 4,
  363. - .frac_bits = 8,
  364. -};
  365. -
  366. -/* TV encoder clock. Only operating frequency is 108Mhz. */
  367. -static const struct bcm2835_clock_data bcm2835_clock_vec_data = {
  368. - .name = "vec",
  369. - .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
  370. - .parents = bcm2835_clock_per_parents,
  371. - .ctl_reg = CM_VECCTL,
  372. - .div_reg = CM_VECDIV,
  373. - .int_bits = 4,
  374. - .frac_bits = 0,
  375. -};
  376. -
  377. -static const struct bcm2835_clock_data bcm2835_clock_uart_data = {
  378. - .name = "uart",
  379. - .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
  380. - .parents = bcm2835_clock_per_parents,
  381. - .ctl_reg = CM_UARTCTL,
  382. - .div_reg = CM_UARTDIV,
  383. - .int_bits = 10,
  384. - .frac_bits = 12,
  385. -};
  386. -
  387. -/* HDMI state machine */
  388. -static const struct bcm2835_clock_data bcm2835_clock_hsm_data = {
  389. - .name = "hsm",
  390. - .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
  391. - .parents = bcm2835_clock_per_parents,
  392. - .ctl_reg = CM_HSMCTL,
  393. - .div_reg = CM_HSMDIV,
  394. - .int_bits = 4,
  395. - .frac_bits = 8,
  396. -};
  397. -
  398. -/*
  399. - * Secondary SDRAM clock. Used for low-voltage modes when the PLL in
  400. - * the SDRAM controller can't be used.
  401. - */
  402. -static const struct bcm2835_clock_data bcm2835_clock_sdram_data = {
  403. - .name = "sdram",
  404. - .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),
  405. - .parents = bcm2835_clock_vpu_parents,
  406. - .ctl_reg = CM_SDCCTL,
  407. - .div_reg = CM_SDCDIV,
  408. - .int_bits = 6,
  409. - .frac_bits = 0,
  410. -};
  411. -
  412. -/* Clock for the temperature sensor. Generally run at 2Mhz, max 5Mhz. */
  413. -static const struct bcm2835_clock_data bcm2835_clock_tsens_data = {
  414. - .name = "tsens",
  415. - .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents),
  416. - .parents = bcm2835_clock_osc_parents,
  417. - .ctl_reg = CM_TSENSCTL,
  418. - .div_reg = CM_TSENSDIV,
  419. - .int_bits = 5,
  420. - .frac_bits = 0,
  421. -};
  422. -
  423. -/* Arasan EMMC clock */
  424. -static const struct bcm2835_clock_data bcm2835_clock_emmc_data = {
  425. - .name = "emmc",
  426. - .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
  427. - .parents = bcm2835_clock_per_parents,
  428. - .ctl_reg = CM_EMMCCTL,
  429. - .div_reg = CM_EMMCDIV,
  430. - .int_bits = 4,
  431. - .frac_bits = 8,
  432. -};
  433. -
  434. -static const struct bcm2835_clock_data bcm2835_clock_pwm_data = {
  435. - .name = "pwm",
  436. - .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
  437. - .parents = bcm2835_clock_per_parents,
  438. - .ctl_reg = CM_PWMCTL,
  439. - .div_reg = CM_PWMDIV,
  440. - .int_bits = 12,
  441. - .frac_bits = 12,
  442. - .is_mash_clock = true,
  443. -};
  444. -
  445. struct bcm2835_gate_data {
  446. const char *name;
  447. const char *parent;
  448. @@ -860,18 +455,6 @@ struct bcm2835_gate_data {
  449. u32 ctl_reg;
  450. };
  451. -/*
  452. - * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if
  453. - * you have the debug bit set in the power manager, which we
  454. - * don't bother exposing) are individual gates off of the
  455. - * non-stop vpu clock.
  456. - */
  457. -static const struct bcm2835_gate_data bcm2835_clock_peri_image_data = {
  458. - .name = "peri_image",
  459. - .parent = "vpu",
  460. - .ctl_reg = CM_PERIICTL,
  461. -};
  462. -
  463. struct bcm2835_pll {
  464. struct clk_hw hw;
  465. struct bcm2835_cprman *cprman;
  466. @@ -1602,7 +1185,7 @@ bcm2835_register_pll_divider(struct bcm2
  467. memset(&init, 0, sizeof(init));
  468. - init.parent_names = &data->source_pll->name;
  469. + init.parent_names = &data->source_pll;
  470. init.num_parents = 1;
  471. init.name = divider_name;
  472. init.ops = &bcm2835_pll_divider_clk_ops;
  473. @@ -1701,50 +1284,401 @@ struct bcm2835_clk_desc {
  474. const void *data;
  475. };
  476. -#define _REGISTER(f, d) { .clk_register = (bcm2835_clk_register)f, \
  477. - .data = d }
  478. -#define REGISTER_PLL(d) _REGISTER(&bcm2835_register_pll, d)
  479. -#define REGISTER_PLL_DIV(d) _REGISTER(&bcm2835_register_pll_divider, d)
  480. -#define REGISTER_CLK(d) _REGISTER(&bcm2835_register_clock, d)
  481. -#define REGISTER_GATE(d) _REGISTER(&bcm2835_register_gate, d)
  482. +/* assignment helper macros for different clock types */
  483. +#define _REGISTER(f, ...) { .clk_register = (bcm2835_clk_register)f, \
  484. + .data = __VA_ARGS__ }
  485. +#define REGISTER_PLL(...) _REGISTER(&bcm2835_register_pll, \
  486. + &(struct bcm2835_pll_data) \
  487. + {__VA_ARGS__})
  488. +#define REGISTER_PLL_DIV(...) _REGISTER(&bcm2835_register_pll_divider, \
  489. + &(struct bcm2835_pll_divider_data) \
  490. + {__VA_ARGS__})
  491. +#define REGISTER_CLK(...) _REGISTER(&bcm2835_register_clock, \
  492. + &(struct bcm2835_clock_data) \
  493. + {__VA_ARGS__})
  494. +#define REGISTER_GATE(...) _REGISTER(&bcm2835_register_gate, \
  495. + &(struct bcm2835_gate_data) \
  496. + {__VA_ARGS__})
  497. +
  498. +/* parent mux arrays plus helper macros */
  499. +
  500. +/* main oscillator parent mux */
  501. +static const char *const bcm2835_clock_osc_parents[] = {
  502. + "gnd",
  503. + "xosc",
  504. + "testdebug0",
  505. + "testdebug1"
  506. +};
  507. +
  508. +#define REGISTER_OSC_CLK(...) REGISTER_CLK( \
  509. + .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), \
  510. + .parents = bcm2835_clock_osc_parents, \
  511. + __VA_ARGS__)
  512. +
  513. +/* main peripherial parent mux */
  514. +static const char *const bcm2835_clock_per_parents[] = {
  515. + "gnd",
  516. + "xosc",
  517. + "testdebug0",
  518. + "testdebug1",
  519. + "plla_per",
  520. + "pllc_per",
  521. + "plld_per",
  522. + "pllh_aux",
  523. +};
  524. +
  525. +#define REGISTER_PER_CLK(...) REGISTER_CLK( \
  526. + .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), \
  527. + .parents = bcm2835_clock_per_parents, \
  528. + __VA_ARGS__)
  529. +
  530. +/* main vpu parent mux */
  531. +static const char *const bcm2835_clock_vpu_parents[] = {
  532. + "gnd",
  533. + "xosc",
  534. + "testdebug0",
  535. + "testdebug1",
  536. + "plla_core",
  537. + "pllc_core0",
  538. + "plld_core",
  539. + "pllh_aux",
  540. + "pllc_core1",
  541. + "pllc_core2",
  542. +};
  543. +
  544. +#define REGISTER_VPU_CLK(...) REGISTER_CLK( \
  545. + .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), \
  546. + .parents = bcm2835_clock_vpu_parents, \
  547. + __VA_ARGS__)
  548. +/*
  549. + * the real definition of all the pll, pll_dividers and clocks
  550. + * these make use of the above REGISTER_* macros
  551. + */
  552. static const struct bcm2835_clk_desc clk_desc_array[] = {
  553. - /* register PLL */
  554. - [BCM2835_PLLA] = REGISTER_PLL(&bcm2835_plla_data),
  555. - [BCM2835_PLLB] = REGISTER_PLL(&bcm2835_pllb_data),
  556. - [BCM2835_PLLC] = REGISTER_PLL(&bcm2835_pllc_data),
  557. - [BCM2835_PLLD] = REGISTER_PLL(&bcm2835_plld_data),
  558. - [BCM2835_PLLH] = REGISTER_PLL(&bcm2835_pllh_data),
  559. - /* the PLL dividers */
  560. - [BCM2835_PLLA_CORE] = REGISTER_PLL_DIV(&bcm2835_plla_core_data),
  561. - [BCM2835_PLLA_PER] = REGISTER_PLL_DIV(&bcm2835_plla_per_data),
  562. - [BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV(&bcm2835_pllc_core0_data),
  563. - [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV(&bcm2835_pllc_core1_data),
  564. - [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV(&bcm2835_pllc_core2_data),
  565. - [BCM2835_PLLC_PER] = REGISTER_PLL_DIV(&bcm2835_pllc_per_data),
  566. - [BCM2835_PLLD_CORE] = REGISTER_PLL_DIV(&bcm2835_plld_core_data),
  567. - [BCM2835_PLLD_PER] = REGISTER_PLL_DIV(&bcm2835_plld_per_data),
  568. - [BCM2835_PLLH_RCAL] = REGISTER_PLL_DIV(&bcm2835_pllh_rcal_data),
  569. - [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV(&bcm2835_pllh_aux_data),
  570. - [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV(&bcm2835_pllh_pix_data),
  571. + /* the PLL + PLL dividers */
  572. +
  573. + /*
  574. + * PLLA is the auxiliary PLL, used to drive the CCP2
  575. + * (Compact Camera Port 2) transmitter clock.
  576. + *
  577. + * It is in the PX LDO power domain, which is on when the
  578. + * AUDIO domain is on.
  579. + */
  580. + [BCM2835_PLLA] = REGISTER_PLL(
  581. + .name = "plla",
  582. + .cm_ctrl_reg = CM_PLLA,
  583. + .a2w_ctrl_reg = A2W_PLLA_CTRL,
  584. + .frac_reg = A2W_PLLA_FRAC,
  585. + .ana_reg_base = A2W_PLLA_ANA0,
  586. + .reference_enable_mask = A2W_XOSC_CTRL_PLLA_ENABLE,
  587. + .lock_mask = CM_LOCK_FLOCKA,
  588. +
  589. + .ana = &bcm2835_ana_default,
  590. +
  591. + .min_rate = 600000000u,
  592. + .max_rate = 2400000000u,
  593. + .max_fb_rate = BCM2835_MAX_FB_RATE),
  594. + [BCM2835_PLLA_CORE] = REGISTER_PLL_DIV(
  595. + .name = "plla_core",
  596. + .source_pll = "plla",
  597. + .cm_reg = CM_PLLA,
  598. + .a2w_reg = A2W_PLLA_CORE,
  599. + .load_mask = CM_PLLA_LOADCORE,
  600. + .hold_mask = CM_PLLA_HOLDCORE,
  601. + .fixed_divider = 1),
  602. + [BCM2835_PLLA_PER] = REGISTER_PLL_DIV(
  603. + .name = "plla_per",
  604. + .source_pll = "plla",
  605. + .cm_reg = CM_PLLA,
  606. + .a2w_reg = A2W_PLLA_PER,
  607. + .load_mask = CM_PLLA_LOADPER,
  608. + .hold_mask = CM_PLLA_HOLDPER,
  609. + .fixed_divider = 1),
  610. +
  611. + /* PLLB is used for the ARM's clock. */
  612. + [BCM2835_PLLB] = REGISTER_PLL(
  613. + .name = "pllb",
  614. + .cm_ctrl_reg = CM_PLLB,
  615. + .a2w_ctrl_reg = A2W_PLLB_CTRL,
  616. + .frac_reg = A2W_PLLB_FRAC,
  617. + .ana_reg_base = A2W_PLLB_ANA0,
  618. + .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE,
  619. + .lock_mask = CM_LOCK_FLOCKB,
  620. +
  621. + .ana = &bcm2835_ana_default,
  622. +
  623. + .min_rate = 600000000u,
  624. + .max_rate = 3000000000u,
  625. + .max_fb_rate = BCM2835_MAX_FB_RATE),
  626. + [BCM2835_PLLB_ARM] = REGISTER_PLL_DIV(
  627. + .name = "pllb_arm",
  628. + .source_pll = "pllb",
  629. + .cm_reg = CM_PLLB,
  630. + .a2w_reg = A2W_PLLB_ARM,
  631. + .load_mask = CM_PLLB_LOADARM,
  632. + .hold_mask = CM_PLLB_HOLDARM,
  633. + .fixed_divider = 1),
  634. +
  635. + /*
  636. + * PLLC is the core PLL, used to drive the core VPU clock.
  637. + *
  638. + * It is in the PX LDO power domain, which is on when the
  639. + * AUDIO domain is on.
  640. + */
  641. + [BCM2835_PLLC] = REGISTER_PLL(
  642. + .name = "pllc",
  643. + .cm_ctrl_reg = CM_PLLC,
  644. + .a2w_ctrl_reg = A2W_PLLC_CTRL,
  645. + .frac_reg = A2W_PLLC_FRAC,
  646. + .ana_reg_base = A2W_PLLC_ANA0,
  647. + .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
  648. + .lock_mask = CM_LOCK_FLOCKC,
  649. +
  650. + .ana = &bcm2835_ana_default,
  651. +
  652. + .min_rate = 600000000u,
  653. + .max_rate = 3000000000u,
  654. + .max_fb_rate = BCM2835_MAX_FB_RATE),
  655. + [BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV(
  656. + .name = "pllc_core0",
  657. + .source_pll = "pllc",
  658. + .cm_reg = CM_PLLC,
  659. + .a2w_reg = A2W_PLLC_CORE0,
  660. + .load_mask = CM_PLLC_LOADCORE0,
  661. + .hold_mask = CM_PLLC_HOLDCORE0,
  662. + .fixed_divider = 1),
  663. + [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV(
  664. + .name = "pllc_core1",
  665. + .source_pll = "pllc",
  666. + .cm_reg = CM_PLLC,
  667. + .a2w_reg = A2W_PLLC_CORE1,
  668. + .load_mask = CM_PLLC_LOADCORE1,
  669. + .hold_mask = CM_PLLC_HOLDCORE1,
  670. + .fixed_divider = 1),
  671. + [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV(
  672. + .name = "pllc_core2",
  673. + .source_pll = "pllc",
  674. + .cm_reg = CM_PLLC,
  675. + .a2w_reg = A2W_PLLC_CORE2,
  676. + .load_mask = CM_PLLC_LOADCORE2,
  677. + .hold_mask = CM_PLLC_HOLDCORE2,
  678. + .fixed_divider = 1),
  679. + [BCM2835_PLLC_PER] = REGISTER_PLL_DIV(
  680. + .name = "pllc_per",
  681. + .source_pll = "pllc",
  682. + .cm_reg = CM_PLLC,
  683. + .a2w_reg = A2W_PLLC_PER,
  684. + .load_mask = CM_PLLC_LOADPER,
  685. + .hold_mask = CM_PLLC_HOLDPER,
  686. + .fixed_divider = 1),
  687. +
  688. + /*
  689. + * PLLD is the display PLL, used to drive DSI display panels.
  690. + *
  691. + * It is in the PX LDO power domain, which is on when the
  692. + * AUDIO domain is on.
  693. + */
  694. + [BCM2835_PLLD] = REGISTER_PLL(
  695. + .name = "plld",
  696. + .cm_ctrl_reg = CM_PLLD,
  697. + .a2w_ctrl_reg = A2W_PLLD_CTRL,
  698. + .frac_reg = A2W_PLLD_FRAC,
  699. + .ana_reg_base = A2W_PLLD_ANA0,
  700. + .reference_enable_mask = A2W_XOSC_CTRL_DDR_ENABLE,
  701. + .lock_mask = CM_LOCK_FLOCKD,
  702. +
  703. + .ana = &bcm2835_ana_default,
  704. +
  705. + .min_rate = 600000000u,
  706. + .max_rate = 2400000000u,
  707. + .max_fb_rate = BCM2835_MAX_FB_RATE),
  708. + [BCM2835_PLLD_CORE] = REGISTER_PLL_DIV(
  709. + .name = "plld_core",
  710. + .source_pll = "plld",
  711. + .cm_reg = CM_PLLD,
  712. + .a2w_reg = A2W_PLLD_CORE,
  713. + .load_mask = CM_PLLD_LOADCORE,
  714. + .hold_mask = CM_PLLD_HOLDCORE,
  715. + .fixed_divider = 1),
  716. + [BCM2835_PLLD_PER] = REGISTER_PLL_DIV(
  717. + .name = "plld_per",
  718. + .source_pll = "plld",
  719. + .cm_reg = CM_PLLD,
  720. + .a2w_reg = A2W_PLLD_PER,
  721. + .load_mask = CM_PLLD_LOADPER,
  722. + .hold_mask = CM_PLLD_HOLDPER,
  723. + .fixed_divider = 1),
  724. +
  725. + /*
  726. + * PLLH is used to supply the pixel clock or the AUX clock for the
  727. + * TV encoder.
  728. + *
  729. + * It is in the HDMI power domain.
  730. + */
  731. + [BCM2835_PLLH] = REGISTER_PLL(
  732. + "pllh",
  733. + .cm_ctrl_reg = CM_PLLH,
  734. + .a2w_ctrl_reg = A2W_PLLH_CTRL,
  735. + .frac_reg = A2W_PLLH_FRAC,
  736. + .ana_reg_base = A2W_PLLH_ANA0,
  737. + .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
  738. + .lock_mask = CM_LOCK_FLOCKH,
  739. +
  740. + .ana = &bcm2835_ana_pllh,
  741. +
  742. + .min_rate = 600000000u,
  743. + .max_rate = 3000000000u,
  744. + .max_fb_rate = BCM2835_MAX_FB_RATE),
  745. + [BCM2835_PLLH_RCAL] = REGISTER_PLL_DIV(
  746. + .name = "pllh_rcal",
  747. + .source_pll = "pllh",
  748. + .cm_reg = CM_PLLH,
  749. + .a2w_reg = A2W_PLLH_RCAL,
  750. + .load_mask = CM_PLLH_LOADRCAL,
  751. + .hold_mask = 0,
  752. + .fixed_divider = 10),
  753. + [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV(
  754. + .name = "pllh_aux",
  755. + .source_pll = "pllh",
  756. + .cm_reg = CM_PLLH,
  757. + .a2w_reg = A2W_PLLH_AUX,
  758. + .load_mask = CM_PLLH_LOADAUX,
  759. + .hold_mask = 0,
  760. + .fixed_divider = 10),
  761. + [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV(
  762. + .name = "pllh_pix",
  763. + .source_pll = "pllh",
  764. + .cm_reg = CM_PLLH,
  765. + .a2w_reg = A2W_PLLH_PIX,
  766. + .load_mask = CM_PLLH_LOADPIX,
  767. + .hold_mask = 0,
  768. + .fixed_divider = 10),
  769. +
  770. /* the clocks */
  771. - [BCM2835_CLOCK_TIMER] = REGISTER_CLK(&bcm2835_clock_timer_data),
  772. - [BCM2835_CLOCK_OTP] = REGISTER_CLK(&bcm2835_clock_otp_data),
  773. - [BCM2835_CLOCK_TSENS] = REGISTER_CLK(&bcm2835_clock_tsens_data),
  774. - [BCM2835_CLOCK_VPU] = REGISTER_CLK(&bcm2835_clock_vpu_data),
  775. - [BCM2835_CLOCK_V3D] = REGISTER_CLK(&bcm2835_clock_v3d_data),
  776. - [BCM2835_CLOCK_ISP] = REGISTER_CLK(&bcm2835_clock_isp_data),
  777. - [BCM2835_CLOCK_H264] = REGISTER_CLK(&bcm2835_clock_h264_data),
  778. - [BCM2835_CLOCK_V3D] = REGISTER_CLK(&bcm2835_clock_v3d_data),
  779. - [BCM2835_CLOCK_SDRAM] = REGISTER_CLK(&bcm2835_clock_sdram_data),
  780. - [BCM2835_CLOCK_UART] = REGISTER_CLK(&bcm2835_clock_uart_data),
  781. - [BCM2835_CLOCK_VEC] = REGISTER_CLK(&bcm2835_clock_vec_data),
  782. - [BCM2835_CLOCK_HSM] = REGISTER_CLK(&bcm2835_clock_hsm_data),
  783. - [BCM2835_CLOCK_EMMC] = REGISTER_CLK(&bcm2835_clock_emmc_data),
  784. - [BCM2835_CLOCK_PWM] = REGISTER_CLK(&bcm2835_clock_pwm_data),
  785. +
  786. + /* clocks with oscillator parent mux */
  787. +
  788. + /* One Time Programmable Memory clock. Maximum 10Mhz. */
  789. + [BCM2835_CLOCK_OTP] = REGISTER_OSC_CLK(
  790. + .name = "otp",
  791. + .ctl_reg = CM_OTPCTL,
  792. + .div_reg = CM_OTPDIV,
  793. + .int_bits = 4,
  794. + .frac_bits = 0),
  795. + /*
  796. + * Used for a 1Mhz clock for the system clocksource, and also used
  797. + * bythe watchdog timer and the camera pulse generator.
  798. + */
  799. + [BCM2835_CLOCK_TIMER] = REGISTER_OSC_CLK(
  800. + .name = "timer",
  801. + .ctl_reg = CM_TIMERCTL,
  802. + .div_reg = CM_TIMERDIV,
  803. + .int_bits = 6,
  804. + .frac_bits = 12),
  805. + /*
  806. + * Clock for the temperature sensor.
  807. + * Generally run at 2Mhz, max 5Mhz.
  808. + */
  809. + [BCM2835_CLOCK_TSENS] = REGISTER_OSC_CLK(
  810. + .name = "tsens",
  811. + .ctl_reg = CM_TSENSCTL,
  812. + .div_reg = CM_TSENSDIV,
  813. + .int_bits = 5,
  814. + .frac_bits = 0),
  815. +
  816. + /* clocks with vpu parent mux */
  817. + [BCM2835_CLOCK_H264] = REGISTER_VPU_CLK(
  818. + .name = "h264",
  819. + .ctl_reg = CM_H264CTL,
  820. + .div_reg = CM_H264DIV,
  821. + .int_bits = 4,
  822. + .frac_bits = 8),
  823. + [BCM2835_CLOCK_ISP] = REGISTER_VPU_CLK(
  824. + .name = "isp",
  825. + .ctl_reg = CM_ISPCTL,
  826. + .div_reg = CM_ISPDIV,
  827. + .int_bits = 4,
  828. + .frac_bits = 8),
  829. + /*
  830. + * Secondary SDRAM clock. Used for low-voltage modes when the PLL
  831. + * in the SDRAM controller can't be used.
  832. + */
  833. + [BCM2835_CLOCK_SDRAM] = REGISTER_VPU_CLK(
  834. + .name = "sdram",
  835. + .ctl_reg = CM_SDCCTL,
  836. + .div_reg = CM_SDCDIV,
  837. + .int_bits = 6,
  838. + .frac_bits = 0),
  839. + [BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK(
  840. + .name = "v3d",
  841. + .ctl_reg = CM_V3DCTL,
  842. + .div_reg = CM_V3DDIV,
  843. + .int_bits = 4,
  844. + .frac_bits = 8),
  845. + /*
  846. + * VPU clock. This doesn't have an enable bit, since it drives
  847. + * the bus for everything else, and is special so it doesn't need
  848. + * to be gated for rate changes. It is also known as "clk_audio"
  849. + * in various hardware documentation.
  850. + */
  851. + [BCM2835_CLOCK_VPU] = REGISTER_VPU_CLK(
  852. + .name = "vpu",
  853. + .ctl_reg = CM_VPUCTL,
  854. + .div_reg = CM_VPUDIV,
  855. + .int_bits = 12,
  856. + .frac_bits = 8,
  857. + .is_vpu_clock = true),
  858. +
  859. + /* clocks with per parent mux */
  860. +
  861. + /* Arasan EMMC clock */
  862. + [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK(
  863. + .name = "emmc",
  864. + .ctl_reg = CM_EMMCCTL,
  865. + .div_reg = CM_EMMCDIV,
  866. + .int_bits = 4,
  867. + .frac_bits = 8),
  868. + /* HDMI state machine */
  869. + [BCM2835_CLOCK_HSM] = REGISTER_PER_CLK(
  870. + .name = "hsm",
  871. + .ctl_reg = CM_HSMCTL,
  872. + .div_reg = CM_HSMDIV,
  873. + .int_bits = 4,
  874. + .frac_bits = 8),
  875. + [BCM2835_CLOCK_PWM] = REGISTER_PER_CLK(
  876. + .name = "pwm",
  877. + .ctl_reg = CM_PWMCTL,
  878. + .div_reg = CM_PWMDIV,
  879. + .int_bits = 12,
  880. + .frac_bits = 12,
  881. + .is_mash_clock = true),
  882. + [BCM2835_CLOCK_UART] = REGISTER_PER_CLK(
  883. + .name = "uart",
  884. + .ctl_reg = CM_UARTCTL,
  885. + .div_reg = CM_UARTDIV,
  886. + .int_bits = 10,
  887. + .frac_bits = 12),
  888. + /* TV encoder clock. Only operating frequency is 108Mhz. */
  889. + [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK(
  890. + .name = "vec",
  891. + .ctl_reg = CM_VECCTL,
  892. + .div_reg = CM_VECDIV,
  893. + .int_bits = 4,
  894. + .frac_bits = 0),
  895. +
  896. /* the gates */
  897. +
  898. + /*
  899. + * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if
  900. + * you have the debug bit set in the power manager, which we
  901. + * don't bother exposing) are individual gates off of the
  902. + * non-stop vpu clock.
  903. + */
  904. [BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE(
  905. - &bcm2835_clock_peri_image_data),
  906. + .name = "peri_image",
  907. + .parent = "vpu",
  908. + .ctl_reg = CM_PERIICTL),
  909. };
  910. static int bcm2835_clk_probe(struct platform_device *pdev)