0262-clk-bcm2835-add-missing-PLL-clock-dividers.patch 2.3 KB

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  1. From 471248ef11464161346bd623becb383625122162 Mon Sep 17 00:00:00 2001
  2. From: Martin Sperl <kernel@martin.sperl.org>
  3. Date: Mon, 29 Feb 2016 15:43:56 +0000
  4. Subject: [PATCH] clk: bcm2835: add missing PLL clock dividers
  5. Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
  6. Signed-off-by: Eric Anholt <eric@anholt.net>
  7. Reviewed-by: Eric Anholt <eric@anholt.net>
  8. (cherry picked from commit 728436956aa172b24a3212295f8b53feb6479f32)
  9. ---
  10. drivers/clk/bcm/clk-bcm2835.c | 32 ++++++++++++++++++++++++++++++++
  11. include/dt-bindings/clock/bcm2835.h | 5 +++++
  12. 2 files changed, 37 insertions(+)
  13. --- a/drivers/clk/bcm/clk-bcm2835.c
  14. +++ b/drivers/clk/bcm/clk-bcm2835.c
  15. @@ -1395,6 +1395,22 @@ static const struct bcm2835_clk_desc clk
  16. .load_mask = CM_PLLA_LOADPER,
  17. .hold_mask = CM_PLLA_HOLDPER,
  18. .fixed_divider = 1),
  19. + [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV(
  20. + .name = "plla_dsi0",
  21. + .source_pll = "plla",
  22. + .cm_reg = CM_PLLA,
  23. + .a2w_reg = A2W_PLLA_DSI0,
  24. + .load_mask = CM_PLLA_LOADDSI0,
  25. + .hold_mask = CM_PLLA_HOLDDSI0,
  26. + .fixed_divider = 1),
  27. + [BCM2835_PLLA_CCP2] = REGISTER_PLL_DIV(
  28. + .name = "plla_ccp2",
  29. + .source_pll = "plla",
  30. + .cm_reg = CM_PLLA,
  31. + .a2w_reg = A2W_PLLA_CCP2,
  32. + .load_mask = CM_PLLA_LOADCCP2,
  33. + .hold_mask = CM_PLLA_HOLDCCP2,
  34. + .fixed_divider = 1),
  35. /* PLLB is used for the ARM's clock. */
  36. [BCM2835_PLLB] = REGISTER_PLL(
  37. @@ -1509,6 +1525,22 @@ static const struct bcm2835_clk_desc clk
  38. .load_mask = CM_PLLD_LOADPER,
  39. .hold_mask = CM_PLLD_HOLDPER,
  40. .fixed_divider = 1),
  41. + [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV(
  42. + .name = "plld_dsi0",
  43. + .source_pll = "plld",
  44. + .cm_reg = CM_PLLD,
  45. + .a2w_reg = A2W_PLLD_DSI0,
  46. + .load_mask = CM_PLLD_LOADDSI0,
  47. + .hold_mask = CM_PLLD_HOLDDSI0,
  48. + .fixed_divider = 1),
  49. + [BCM2835_PLLD_DSI1] = REGISTER_PLL_DIV(
  50. + .name = "plld_dsi1",
  51. + .source_pll = "plld",
  52. + .cm_reg = CM_PLLD,
  53. + .a2w_reg = A2W_PLLD_DSI1,
  54. + .load_mask = CM_PLLD_LOADDSI1,
  55. + .hold_mask = CM_PLLD_HOLDDSI1,
  56. + .fixed_divider = 1),
  57. /*
  58. * PLLH is used to supply the pixel clock or the AUX clock for the
  59. --- a/include/dt-bindings/clock/bcm2835.h
  60. +++ b/include/dt-bindings/clock/bcm2835.h
  61. @@ -45,3 +45,8 @@
  62. #define BCM2835_CLOCK_PERI_IMAGE 29
  63. #define BCM2835_CLOCK_PWM 30
  64. #define BCM2835_CLOCK_PCM 31
  65. +
  66. +#define BCM2835_PLLA_DSI0 32
  67. +#define BCM2835_PLLA_CCP2 33
  68. +#define BCM2835_PLLD_DSI0 34
  69. +#define BCM2835_PLLD_DSI1 35