0289-drm-vc4-Initialize-scaler-DISPBKGND-on-modeset.patch 2.7 KB

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  1. From a8aa07e1bf9d48e8f47a873062080c7fd2f05a25 Mon Sep 17 00:00:00 2001
  2. From: Eric Anholt <eric@anholt.net>
  3. Date: Tue, 16 Feb 2016 10:24:08 -0800
  4. Subject: [PATCH] drm/vc4: Initialize scaler DISPBKGND on modeset.
  5. We weren't updating the interlaced bit, so we'd scan out incorrectly
  6. if the firmware had brought up the TV encoder and we were switching to
  7. HDMI.
  8. Signed-off-by: Eric Anholt <eric@anholt.net>
  9. (cherry picked from commit 6a609209865247cc748e90158c99f374f79b494c)
  10. ---
  11. drivers/gpu/drm/vc4/vc4_crtc.c | 6 ++++++
  12. drivers/gpu/drm/vc4/vc4_regs.h | 14 ++++++++++++++
  13. 2 files changed, 20 insertions(+)
  14. --- a/drivers/gpu/drm/vc4/vc4_crtc.c
  15. +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
  16. @@ -188,6 +188,8 @@ static int vc4_get_clock_select(struct d
  17. static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
  18. {
  19. + struct drm_device *dev = crtc->dev;
  20. + struct vc4_dev *vc4 = to_vc4_dev(dev);
  21. struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
  22. struct drm_crtc_state *state = crtc->state;
  23. struct drm_display_mode *mode = &state->adjusted_mode;
  24. @@ -256,6 +258,10 @@ static void vc4_crtc_mode_set_nofb(struc
  25. PV_CONTROL_FIFO_CLR |
  26. PV_CONTROL_EN);
  27. + HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
  28. + SCALER_DISPBKGND_AUTOHS |
  29. + (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
  30. +
  31. if (debug_dump_regs) {
  32. DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc));
  33. vc4_crtc_dump_regs(vc4_crtc);
  34. --- a/drivers/gpu/drm/vc4/vc4_regs.h
  35. +++ b/drivers/gpu/drm/vc4/vc4_regs.h
  36. @@ -350,6 +350,17 @@
  37. # define SCALER_DISPCTRLX_HEIGHT_SHIFT 0
  38. #define SCALER_DISPBKGND0 0x00000044
  39. +# define SCALER_DISPBKGND_AUTOHS BIT(31)
  40. +# define SCALER_DISPBKGND_INTERLACE BIT(30)
  41. +# define SCALER_DISPBKGND_GAMMA BIT(29)
  42. +# define SCALER_DISPBKGND_TESTMODE_MASK VC4_MASK(28, 25)
  43. +# define SCALER_DISPBKGND_TESTMODE_SHIFT 25
  44. +/* Enables filling the scaler line with the RGB value in the low 24
  45. + * bits before compositing. Costs cycles, so should be skipped if
  46. + * opaque display planes will cover everything.
  47. + */
  48. +# define SCALER_DISPBKGND_FILL BIT(24)
  49. +
  50. #define SCALER_DISPSTAT0 0x00000048
  51. #define SCALER_DISPBASE0 0x0000004c
  52. # define SCALER_DISPSTATX_MODE_MASK VC4_MASK(31, 30)
  53. @@ -362,6 +373,9 @@
  54. # define SCALER_DISPSTATX_EMPTY BIT(28)
  55. #define SCALER_DISPCTRL1 0x00000050
  56. #define SCALER_DISPBKGND1 0x00000054
  57. +#define SCALER_DISPBKGNDX(x) (SCALER_DISPBKGND0 + \
  58. + (x) * (SCALER_DISPBKGND1 - \
  59. + SCALER_DISPBKGND0))
  60. #define SCALER_DISPSTAT1 0x00000058
  61. #define SCALER_DISPSTATX(x) (SCALER_DISPSTAT0 + \
  62. (x) * (SCALER_DISPSTAT1 - \