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patches-4.4
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110-pci_isolated_interrupts.patch

110-pci_isolated_interrupts.patch 2.9 KB
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  1. --- a/arch/arm/mach-cns3xxx/pcie.c
    2. 

  2. +++ b/arch/arm/mach-cns3xxx/pcie.c
    3. 

  3. @@ -18,6 +18,7 @@
    4. 

  4.  #include <linux/io.h>
    5. 

  5.  #include <linux/ioport.h>
    6. 

  6.  #include <linux/interrupt.h>
    7. 

  7. +#include <linux/irq.h>
    8. 

  8.  #include <linux/ptrace.h>
    9. 

  9.  #include <asm/mach/map.h>
    10. 

  10.  #include "cns3xxx.h"
    11. 

  11. @@ -27,7 +28,7 @@ struct cns3xxx_pcie {
    12. 

  12.  	void __iomem *host_regs; /* PCI config registers for host bridge */
    13. 

  13.  	void __iomem *cfg0_regs; /* PCI Type 0 config registers */
    14. 

  14.  	void __iomem *cfg1_regs; /* PCI Type 1 config registers */
    15. 

  15. -	unsigned int irqs[2];
    16. 

  16. +	unsigned int irqs[5];
    17. 

  17.  	struct resource res_io;
    18. 

  18.  	struct resource res_mem;
    19. 

  19.  	int port;
    20. 

  20. @@ -95,7 +96,7 @@ static inline int check_master_abort(str
    21. 

  21.  		void __iomem *host_base;
    22. 

  22.  		u32 sreg, ereg;
    23. 

  23.  
    24. 

  24. -		host_base = (void __iomem *) cnspci->cfg_bases[CNS3XXX_HOST_TYPE].virtual;
    25. 

  25. +		host_base = (void __iomem *) cnspci->host_regs;
    26. 

  26.  		sreg = __raw_readw(host_base + 0x6) & 0xF900;
    27. 

  27.  		ereg = __raw_readl(host_base + 0x104); // Uncorrectable Error Status Reg
    28. 

  28.  
    29. 

  29. @@ -209,7 +210,7 @@ static struct pci_ops cns3xxx_pcie_ops =
    30. 

  30.  static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
    31. 

  31.  {
    32. 

  32.  	struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
    33. 

  33. -	int irq = cnspci->irqs[!!dev->bus->number];
    34. 

  34. +	int irq = cnspci->irqs[!!dev->bus->number + pin - 1];
    35. 

  35.  
    36. 

  36.  	pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n",
    37. 

  37.  		pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn),
    38. 

  38. @@ -235,7 +236,13 @@ static struct cns3xxx_pcie cns3xxx_pcie[
    39. 

  39.  			.end = CNS3XXX_PCIE0_HOST_BASE - 1, /* 176 MiB */
    40. 

  40.  			.flags = IORESOURCE_MEM,
    41. 

  41.  		},
    42. 

  42. -		.irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, },
    43. 

  43. +		.irqs = {
    44. 

  44. +			IRQ_CNS3XXX_PCIE0_RC,
    45. 

  45. +			IRQ_CNS3XXX_PCIE0_DEVICE,
    46. 

  46. +			IRQ_CNS3XXX_PCIE0_DEVICE,
    47. 

  47. +			IRQ_CNS3XXX_PCIE0_DEVICE,
    48. 

  48. +			IRQ_CNS3XXX_PCIE0_DEVICE,
    49. 

  49. +		},
    50. 

  50.  		.port = 0,
    51. 

  51.  	},
    52. 

  52.  	[1] = {
    53. 

  53. @@ -254,7 +261,13 @@ static struct cns3xxx_pcie cns3xxx_pcie[
    54. 

  54.  			.end = CNS3XXX_PCIE1_HOST_BASE - 1, /* 176 MiB */
    55. 

  55.  			.flags = IORESOURCE_MEM,
    56. 

  56.  		},
    57. 

  57. -		.irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, },
    58. 

  58. +		.irqs = {
    59. 

  59. +			IRQ_CNS3XXX_PCIE1_RC,
    60. 

  60. +			IRQ_CNS3XXX_PCIE1_DEVICE,
    61. 

  61. +			IRQ_CNS3XXX_PCIE1_DEVICE,
    62. 

  62. +			IRQ_CNS3XXX_PCIE1_DEVICE,
    63. 

  63. +			IRQ_CNS3XXX_PCIE1_DEVICE,
    64. 

  64. +		},
    65. 

  65.  		.port = 1,
    66. 

  66.  	},
    67. 

  67.  };
    68. 

  68. @@ -346,6 +359,14 @@ static int cns3xxx_pcie_abort_handler(un
    69. 

  69.  	return 0;
    70. 

  70.  }
    71. 

  71.  
    72. 

  72. +void __init cns3xxx_pcie_set_irqs(int bus, int *irqs)
    73. 

  73. +{
    74. 

  74. +	int i;
    75. 

  75. +
    76. 

  76. +	for (i = 0; i < 4; i++)
    77. 

  77. +		cns3xxx_pcie[bus].irqs[i + 1] = irqs[i];
    78. 

  78. +}
    79. 

  79. +
    80. 

  80.  void __init cns3xxx_pcie_init_late(void)
    81. 

  81.  {
    82. 

  82.  	int i;
    83. 

  83. --- a/arch/arm/mach-cns3xxx/core.h
    84. 

  84. +++ b/arch/arm/mach-cns3xxx/core.h
    85. 

  85. @@ -18,8 +18,10 @@ extern void cns3xxx_timer_init(void);
    86. 

  86.  
    87. 

  87.  #ifdef CONFIG_PCI
    88. 

  88.  extern void __init cns3xxx_pcie_init_late(void);
    89. 

  89. +extern void __init cns3xxx_pcie_set_irqs(int bus, int *irqs);
    90. 

  90.  #else
    91. 

  91.  static inline void __init cns3xxx_pcie_init_late(void) {}
    92. 

  92. +static inline void cns3xxx_pcie_set_irqs(int bus, int *irqs) {}
    93. 

  93.  #endif
    94. 

  94.  
    95. 

  95.  void __init cns3xxx_map_io(void);
    96.