0301-xrx200-add-gphy-clk-src-device-tree-binding.patch 731 B

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  1. --- a/arch/mips/lantiq/xway/sysctrl.c
  2. +++ b/arch/mips/lantiq/xway/sysctrl.c
  3. @@ -442,6 +442,20 @@ static void clkdev_add_clkout(void)
  4. }
  5. }
  6. +static void set_phy_clock_source(struct device_node *np_cgu)
  7. +{
  8. + u32 phy_clk_src, ifcc;
  9. +
  10. + if (!np_cgu)
  11. + return;
  12. +
  13. + if (of_property_read_u32(np_cgu, "lantiq,phy-clk-src", &phy_clk_src))
  14. + return;
  15. +
  16. + ifcc = ltq_cgu_r32(ifccr) & ~(0x1c);
  17. + ltq_cgu_w32(ifcc | (phy_clk_src << 2), ifccr);
  18. +}
  19. +
  20. /* bring up all register ranges that we need for basic system control */
  21. void __init ltq_soc_init(void)
  22. {
  23. @@ -628,4 +642,6 @@ void __init ltq_soc_init(void)
  24. if (of_machine_is_compatible("lantiq,vr9"))
  25. xbar_fpi_burst_disable();
  26. usb_set_clock();
  27. +
  28. + set_phy_clock_source(np_cgu);
  29. }