ZBT-APE522II.dts 2.1 KB

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  1. /dts-v1/;
  2. #include "mt7620a.dtsi"
  3. #include <dt-bindings/input/input.h>
  4. / {
  5. compatible = "zbtlink,zbt-ape522ii", "ralink,mt7620a-soc";
  6. model = "ZBT-APE522II";
  7. chosen {
  8. bootargs = "console=ttyS0,115200";
  9. };
  10. gpio-leds {
  11. compatible = "gpio-leds";
  12. sys1 {
  13. label = "zbt-ape522ii:green:sys1";
  14. gpios = <&gpio0 11 1>;
  15. };
  16. sys2 {
  17. label = "zbt-ape522ii:green:sys2";
  18. gpios = <&gpio0 12 1>;
  19. };
  20. sys3 {
  21. label = "zbt-ape522ii:green:sys3";
  22. gpios = <&gpio0 9 1>;
  23. };
  24. sys4 {
  25. label = "zbt-ape522ii:green:sys4";
  26. gpios = <&gpio0 14 1>;
  27. };
  28. wlan2g4 {
  29. label = "zbt-ape522ii:green:wlan2g4";
  30. gpios = <&gpio3 0 1>;
  31. };
  32. };
  33. gpio-keys-polled {
  34. compatible = "gpio-keys-polled";
  35. #address-cells = <1>;
  36. #size-cells = <0>;
  37. poll-interval = <20>;
  38. reset {
  39. label = "reset";
  40. gpios = <&gpio0 2 0>;
  41. linux,code = <KEY_RESTART>;
  42. };
  43. };
  44. };
  45. &gpio0 {
  46. status = "okay";
  47. };
  48. &gpio1 {
  49. status = "okay";
  50. };
  51. &gpio2 {
  52. status = "okay";
  53. };
  54. &gpio3 {
  55. status = "okay";
  56. };
  57. &spi0 {
  58. status = "okay";
  59. m25p80@0 {
  60. #address-cells = <1>;
  61. #size-cells = <1>;
  62. compatible = "jedec,spi-nor";
  63. reg = <0>;
  64. spi-max-frequency = <10000000>;
  65. partition@0 {
  66. label = "u-boot";
  67. reg = <0x0 0x30000>;
  68. };
  69. partition@30000 {
  70. label = "u-boot-env";
  71. reg = <0x30000 0x10000>;
  72. read-only;
  73. };
  74. factory: partition@40000 {
  75. label = "factory";
  76. reg = <0x40000 0x10000>;
  77. read-only;
  78. };
  79. partition@50000 {
  80. label = "firmware";
  81. reg = <0x50000 0xf80000>;
  82. };
  83. };
  84. };
  85. &ethernet {
  86. pinctrl-names = "default";
  87. pinctrl-0 = <&ephy_pins>;
  88. mtd-mac-address = <&factory 0x4>;
  89. mediatek,portmap = "wllll";
  90. };
  91. &wmac {
  92. ralink,mtd-eeprom = <&factory 0>;
  93. };
  94. &pcie {
  95. status = "okay";
  96. pcie-bridge {
  97. mt76@0,0 {
  98. reg = <0x0000 0 0 0 0>;
  99. device_type = "pci";
  100. mediatek,mtd-eeprom = <&factory 0x8000>;
  101. ieee80211-freq-limit = <5000000 6000000>;
  102. };
  103. };
  104. };
  105. &pinctrl {
  106. state_default: pinctrl0 {
  107. gpio {
  108. ralink,group = "wled", "i2c", "uartf", "wdt";
  109. ralink,function = "gpio";
  110. };
  111. pa {
  112. ralink,group = "pa";
  113. ralink,function = "pa";
  114. };
  115. };
  116. };