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@@ -3,31 +3,31 @@ optiboot_atmega1280.elf: file format elf32-avr
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Sections:
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Sections:
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Idx Name Size VMA LMA File off Algn
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Idx Name Size VMA LMA File off Algn
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- 0 .text 0000025c 0001fc00 0001fc00 00000074 2**1
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+ 0 .text 00000264 0001fc00 0001fc00 00000074 2**1
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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- 1 .version 00000002 0001fffe 0001fffe 000002d0 2**0
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- CONTENTS, ALLOC, LOAD, DATA
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- 2 .stab 00000180 00000000 00000000 000002d4 2**2
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+ 1 .version 00000002 0001fffe 0001fffe 000002d8 2**0
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+ CONTENTS, ALLOC, LOAD, READONLY, DATA
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+ 2 .stab 00000180 00000000 00000000 000002dc 2**2
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CONTENTS, READONLY, DEBUGGING
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CONTENTS, READONLY, DEBUGGING
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- 3 .stabstr 000000bb 00000000 00000000 00000454 2**0
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+ 3 .stabstr 000000bb 00000000 00000000 0000045c 2**0
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CONTENTS, READONLY, DEBUGGING
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CONTENTS, READONLY, DEBUGGING
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- 4 .debug_aranges 00000028 00000000 00000000 0000050f 2**0
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+ 4 .debug_aranges 00000028 00000000 00000000 00000517 2**0
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CONTENTS, READONLY, DEBUGGING
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CONTENTS, READONLY, DEBUGGING
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- 5 .debug_pubnames 00000074 00000000 00000000 00000537 2**0
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+ 5 .debug_pubnames 00000074 00000000 00000000 0000053f 2**0
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CONTENTS, READONLY, DEBUGGING
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CONTENTS, READONLY, DEBUGGING
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- 6 .debug_info 000003df 00000000 00000000 000005ab 2**0
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+ 6 .debug_info 000003e4 00000000 00000000 000005b3 2**0
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CONTENTS, READONLY, DEBUGGING
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CONTENTS, READONLY, DEBUGGING
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- 7 .debug_abbrev 000001ea 00000000 00000000 0000098a 2**0
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+ 7 .debug_abbrev 000001f1 00000000 00000000 00000997 2**0
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CONTENTS, READONLY, DEBUGGING
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CONTENTS, READONLY, DEBUGGING
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- 8 .debug_line 0000044b 00000000 00000000 00000b74 2**0
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+ 8 .debug_line 0000045b 00000000 00000000 00000b88 2**0
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CONTENTS, READONLY, DEBUGGING
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CONTENTS, READONLY, DEBUGGING
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- 9 .debug_frame 00000080 00000000 00000000 00000fc0 2**2
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+ 9 .debug_frame 00000080 00000000 00000000 00000fe4 2**2
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CONTENTS, READONLY, DEBUGGING
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CONTENTS, READONLY, DEBUGGING
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- 10 .debug_str 00000172 00000000 00000000 00001040 2**0
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+ 10 .debug_str 00000172 00000000 00000000 00001064 2**0
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CONTENTS, READONLY, DEBUGGING
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CONTENTS, READONLY, DEBUGGING
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- 11 .debug_loc 000003b3 00000000 00000000 000011b2 2**0
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+ 11 .debug_loc 000003b3 00000000 00000000 000011d6 2**0
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CONTENTS, READONLY, DEBUGGING
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CONTENTS, READONLY, DEBUGGING
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- 12 .debug_ranges 000000d0 00000000 00000000 00001565 2**0
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+ 12 .debug_ranges 000000d0 00000000 00000000 00001589 2**0
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CONTENTS, READONLY, DEBUGGING
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CONTENTS, READONLY, DEBUGGING
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Disassembly of section .text:
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Disassembly of section .text:
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@@ -40,640 +40,646 @@ Disassembly of section .text:
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/* main program starts here */
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/* main program starts here */
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int main(void) {
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int main(void) {
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1fc00: 11 24 eor r1, r1
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1fc00: 11 24 eor r1, r1
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-#if defined(__AVR_ATmega8__) || defined (__AVR_ATmega32__)
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- SP=RAMEND; // This is done by hardware reset
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-#endif
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-
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- // Adaboot no-wait mod
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+ * modified Adaboot no-wait mod.
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+ * Pass the reset reason to app. Also, it appears that an Uno poweron
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+ * can leave multiple reset flags set; we only want the bootloader to
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+ * run on an 'external reset only' status
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+ */
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ch = MCUSR;
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ch = MCUSR;
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- 1fc02: 84 b7 in r24, 0x34 ; 52
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+ 1fc02: 94 b7 in r25, 0x34 ; 52
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MCUSR = 0;
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MCUSR = 0;
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1fc04: 14 be out 0x34, r1 ; 52
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1fc04: 14 be out 0x34, r1 ; 52
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- if (!(ch & _BV(EXTRF))) appStart(ch);
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- 1fc06: 81 fd sbrc r24, 1
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- 1fc08: 01 c0 rjmp .+2 ; 0x1fc0c <main+0xc>
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- 1fc0a: 0c d1 rcall .+536 ; 0x1fe24 <appStart>
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+ if (ch & (_BV(WDRF) | _BV(BORF) | _BV(PORF)))
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+ 1fc06: 89 2f mov r24, r25
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+ 1fc08: 8d 70 andi r24, 0x0D ; 13
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+ 1fc0a: 11 f0 breq .+4 ; 0x1fc10 <main+0x10>
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+ appStart(ch);
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+ 1fc0c: 89 2f mov r24, r25
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+ 1fc0e: 0e d1 rcall .+540 ; 0x1fe2c <appStart>
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#if LED_START_FLASHES > 0
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#if LED_START_FLASHES > 0
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// Set up Timer 1 for timeout counter
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// Set up Timer 1 for timeout counter
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TCCR1B = _BV(CS12) | _BV(CS10); // div 1024
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TCCR1B = _BV(CS12) | _BV(CS10); // div 1024
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- 1fc0c: 85 e0 ldi r24, 0x05 ; 5
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- 1fc0e: 80 93 81 00 sts 0x0081, r24
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+ 1fc10: 85 e0 ldi r24, 0x05 ; 5
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+ 1fc12: 80 93 81 00 sts 0x0081, r24
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UCSRA = _BV(U2X); //Double speed mode USART
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UCSRA = _BV(U2X); //Double speed mode USART
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UCSRB = _BV(RXEN) | _BV(TXEN); // enable Rx & Tx
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UCSRB = _BV(RXEN) | _BV(TXEN); // enable Rx & Tx
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UCSRC = _BV(URSEL) | _BV(UCSZ1) | _BV(UCSZ0); // config USART; 8N1
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UCSRC = _BV(URSEL) | _BV(UCSZ1) | _BV(UCSZ0); // config USART; 8N1
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UBRRL = (uint8_t)( (F_CPU + BAUD_RATE * 4L) / (BAUD_RATE * 8L) - 1 );
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UBRRL = (uint8_t)( (F_CPU + BAUD_RATE * 4L) / (BAUD_RATE * 8L) - 1 );
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#else
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#else
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UART_SRA = _BV(U2X0); //Double speed mode USART0
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UART_SRA = _BV(U2X0); //Double speed mode USART0
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- 1fc12: 82 e0 ldi r24, 0x02 ; 2
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- 1fc14: 80 93 c0 00 sts 0x00C0, r24
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+ 1fc16: 82 e0 ldi r24, 0x02 ; 2
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+ 1fc18: 80 93 c0 00 sts 0x00C0, r24
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UART_SRB = _BV(RXEN0) | _BV(TXEN0);
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UART_SRB = _BV(RXEN0) | _BV(TXEN0);
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- 1fc18: 88 e1 ldi r24, 0x18 ; 24
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- 1fc1a: 80 93 c1 00 sts 0x00C1, r24
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+ 1fc1c: 88 e1 ldi r24, 0x18 ; 24
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+ 1fc1e: 80 93 c1 00 sts 0x00C1, r24
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UART_SRC = _BV(UCSZ00) | _BV(UCSZ01);
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UART_SRC = _BV(UCSZ00) | _BV(UCSZ01);
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- 1fc1e: 86 e0 ldi r24, 0x06 ; 6
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- 1fc20: 80 93 c2 00 sts 0x00C2, r24
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+ 1fc22: 86 e0 ldi r24, 0x06 ; 6
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+ 1fc24: 80 93 c2 00 sts 0x00C2, r24
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UART_SRL = (uint8_t)( (F_CPU + BAUD_RATE * 4L) / (BAUD_RATE * 8L) - 1 );
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UART_SRL = (uint8_t)( (F_CPU + BAUD_RATE * 4L) / (BAUD_RATE * 8L) - 1 );
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- 1fc24: 80 e1 ldi r24, 0x10 ; 16
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- 1fc26: 80 93 c4 00 sts 0x00C4, r24
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+ 1fc28: 80 e1 ldi r24, 0x10 ; 16
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+ 1fc2a: 80 93 c4 00 sts 0x00C4, r24
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#endif
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#endif
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#endif
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#endif
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// Set up watchdog to trigger after 500ms
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// Set up watchdog to trigger after 500ms
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watchdogConfig(WATCHDOG_1S);
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watchdogConfig(WATCHDOG_1S);
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- 1fc2a: 8e e0 ldi r24, 0x0E ; 14
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- 1fc2c: e5 d0 rcall .+458 ; 0x1fdf8 <watchdogConfig>
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+ 1fc2e: 8e e0 ldi r24, 0x0E ; 14
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+ 1fc30: e7 d0 rcall .+462 ; 0x1fe00 <watchdogConfig>
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#if (LED_START_FLASHES > 0) || defined(LED_DATA_FLASH)
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#if (LED_START_FLASHES > 0) || defined(LED_DATA_FLASH)
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/* Set LED pin as output */
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/* Set LED pin as output */
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LED_DDR |= _BV(LED);
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LED_DDR |= _BV(LED);
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- 1fc2e: 27 9a sbi 0x04, 7 ; 4
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- 1fc30: 86 e0 ldi r24, 0x06 ; 6
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+ 1fc32: 27 9a sbi 0x04, 7 ; 4
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+ 1fc34: 86 e0 ldi r24, 0x06 ; 6
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}
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}
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#if LED_START_FLASHES > 0
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#if LED_START_FLASHES > 0
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void flash_led(uint8_t count) {
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void flash_led(uint8_t count) {
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do {
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do {
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TCNT1 = -(F_CPU/(1024*16));
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TCNT1 = -(F_CPU/(1024*16));
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- 1fc32: 20 e3 ldi r18, 0x30 ; 48
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- 1fc34: 3c ef ldi r19, 0xFC ; 252
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+ 1fc36: 20 e3 ldi r18, 0x30 ; 48
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+ 1fc38: 3c ef ldi r19, 0xFC ; 252
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TIFR1 = _BV(TOV1);
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TIFR1 = _BV(TOV1);
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- 1fc36: 91 e0 ldi r25, 0x01 ; 1
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+ 1fc3a: 91 e0 ldi r25, 0x01 ; 1
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}
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}
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#if LED_START_FLASHES > 0
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#if LED_START_FLASHES > 0
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void flash_led(uint8_t count) {
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void flash_led(uint8_t count) {
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do {
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do {
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TCNT1 = -(F_CPU/(1024*16));
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TCNT1 = -(F_CPU/(1024*16));
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- 1fc38: 30 93 85 00 sts 0x0085, r19
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- 1fc3c: 20 93 84 00 sts 0x0084, r18
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+ 1fc3c: 30 93 85 00 sts 0x0085, r19
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+ 1fc40: 20 93 84 00 sts 0x0084, r18
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TIFR1 = _BV(TOV1);
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TIFR1 = _BV(TOV1);
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- 1fc40: 96 bb out 0x16, r25 ; 22
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+ 1fc44: 96 bb out 0x16, r25 ; 22
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while(!(TIFR1 & _BV(TOV1)));
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while(!(TIFR1 & _BV(TOV1)));
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- 1fc42: b0 9b sbis 0x16, 0 ; 22
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- 1fc44: fe cf rjmp .-4 ; 0x1fc42 <main+0x42>
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+ 1fc46: b0 9b sbis 0x16, 0 ; 22
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+ 1fc48: fe cf rjmp .-4 ; 0x1fc46 <main+0x46>
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#if defined(__AVR_ATmega8__) || defined (__AVR_ATmega32__)
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#if defined(__AVR_ATmega8__) || defined (__AVR_ATmega32__)
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LED_PORT ^= _BV(LED);
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LED_PORT ^= _BV(LED);
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#else
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#else
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LED_PIN |= _BV(LED);
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LED_PIN |= _BV(LED);
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- 1fc46: 1f 9a sbi 0x03, 7 ; 3
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+ 1fc4a: 1f 9a sbi 0x03, 7 ; 3
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}
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}
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#endif
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#endif
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// Watchdog functions. These are only safe with interrupts turned off.
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// Watchdog functions. These are only safe with interrupts turned off.
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void watchdogReset() {
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void watchdogReset() {
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__asm__ __volatile__ (
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__asm__ __volatile__ (
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- 1fc48: a8 95 wdr
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+ 1fc4c: a8 95 wdr
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LED_PORT ^= _BV(LED);
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LED_PORT ^= _BV(LED);
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#else
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#else
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LED_PIN |= _BV(LED);
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LED_PIN |= _BV(LED);
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#endif
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#endif
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watchdogReset();
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watchdogReset();
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} while (--count);
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} while (--count);
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- 1fc4a: 81 50 subi r24, 0x01 ; 1
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- 1fc4c: a9 f7 brne .-22 ; 0x1fc38 <main+0x38>
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- 1fc4e: cc 24 eor r12, r12
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- 1fc50: dd 24 eor r13, r13
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+ 1fc4e: 81 50 subi r24, 0x01 ; 1
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+ 1fc50: a9 f7 brne .-22 ; 0x1fc3c <main+0x3c>
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+ 1fc52: cc 24 eor r12, r12
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+ 1fc54: dd 24 eor r13, r13
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*/
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*/
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do {
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do {
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uint16_t a;
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uint16_t a;
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a = *bufPtr++;
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a = *bufPtr++;
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a |= (*bufPtr++) << 8;
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a |= (*bufPtr++) << 8;
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__boot_page_fill_short((uint16_t)(void*)addrPtr,a);
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__boot_page_fill_short((uint16_t)(void*)addrPtr,a);
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- 1fc52: 88 24 eor r8, r8
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- 1fc54: 83 94 inc r8
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+ 1fc56: 88 24 eor r8, r8
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+ 1fc58: 83 94 inc r8
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} while (len -= 2);
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} while (len -= 2);
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/*
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/*
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* Actually Write the buffer to flash (and wait for it to finish.)
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* Actually Write the buffer to flash (and wait for it to finish.)
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*/
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*/
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__boot_page_write_short((uint16_t)(void*)address);
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__boot_page_write_short((uint16_t)(void*)address);
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- 1fc56: 25 e0 ldi r18, 0x05 ; 5
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- 1fc58: a2 2e mov r10, r18
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+ 1fc5a: 25 e0 ldi r18, 0x05 ; 5
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+ 1fc5c: a2 2e mov r10, r18
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boot_spm_busy_wait();
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boot_spm_busy_wait();
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#if defined(RWWSRE)
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#if defined(RWWSRE)
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// Reenable read access to flash
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// Reenable read access to flash
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boot_rww_enable();
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boot_rww_enable();
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- 1fc5a: 91 e1 ldi r25, 0x11 ; 17
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- 1fc5c: 99 2e mov r9, r25
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+ 1fc5e: 91 e1 ldi r25, 0x11 ; 17
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+ 1fc60: 99 2e mov r9, r25
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#endif
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#endif
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/* Forever loop: exits by causing WDT reset */
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/* Forever loop: exits by causing WDT reset */
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for (;;) {
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for (;;) {
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/* get character from UART */
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/* get character from UART */
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ch = getch();
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ch = getch();
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- 1fc5e: c0 d0 rcall .+384 ; 0x1fde0 <getch>
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+ 1fc62: c2 d0 rcall .+388 ; 0x1fde8 <getch>
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if(ch == STK_GET_PARAMETER) {
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if(ch == STK_GET_PARAMETER) {
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- 1fc60: 81 34 cpi r24, 0x41 ; 65
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- 1fc62: 61 f4 brne .+24 ; 0x1fc7c <main+0x7c>
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+ 1fc64: 81 34 cpi r24, 0x41 ; 65
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+ 1fc66: 71 f4 brne .+28 ; 0x1fc84 <main+0x84>
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unsigned char which = getch();
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unsigned char which = getch();
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- 1fc64: bd d0 rcall .+378 ; 0x1fde0 <getch>
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- 1fc66: 18 2f mov r17, r24
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+ 1fc68: bf d0 rcall .+382 ; 0x1fde8 <getch>
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+ 1fc6a: 18 2f mov r17, r24
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verifySpace();
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verifySpace();
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- 1fc68: cd d0 rcall .+410 ; 0x1fe04 <verifySpace>
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+ 1fc6c: cf d0 rcall .+414 ; 0x1fe0c <verifySpace>
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+ /*
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+ * Send optiboot version as "SW version"
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+ * Note that the references to memory are optimized away.
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+ */
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if (which == 0x82) {
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if (which == 0x82) {
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- 1fc6a: 12 38 cpi r17, 0x82 ; 130
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- 1fc6c: 51 f1 breq .+84 ; 0x1fcc2 <main+0xc2>
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- /*
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- * Send optiboot version as "minor SW version"
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- */
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- putch(OPTIBOOT_MINVER);
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- } else if (which == 0x81) {
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- 1fc6e: 11 38 cpi r17, 0x81 ; 129
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+ 1fc6e: 12 38 cpi r17, 0x82 ; 130
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1fc70: 11 f4 brne .+4 ; 0x1fc76 <main+0x76>
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1fc70: 11 f4 brne .+4 ; 0x1fc76 <main+0x76>
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- putch(OPTIBOOT_MAJVER);
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- 1fc72: 86 e0 ldi r24, 0x06 ; 6
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- 1fc74: 01 c0 rjmp .+2 ; 0x1fc78 <main+0x78>
|
|
|
|
|
|
+ putch(optiboot_version & 0xFF);
|
|
|
|
+ 1fc72: 81 e0 ldi r24, 0x01 ; 1
|
|
|
|
+ 1fc74: 05 c0 rjmp .+10 ; 0x1fc80 <main+0x80>
|
|
|
|
+ } else if (which == 0x81) {
|
|
|
|
+ 1fc76: 11 38 cpi r17, 0x81 ; 129
|
|
|
|
+ 1fc78: 11 f4 brne .+4 ; 0x1fc7e <main+0x7e>
|
|
|
|
+ putch(optiboot_version >> 8);
|
|
|
|
+ 1fc7a: 86 e0 ldi r24, 0x06 ; 6
|
|
|
|
+ 1fc7c: 01 c0 rjmp .+2 ; 0x1fc80 <main+0x80>
|
|
} else {
|
|
} else {
|
|
/*
|
|
/*
|
|
* GET PARAMETER returns a generic 0x03 reply for
|
|
* GET PARAMETER returns a generic 0x03 reply for
|
|
* other parameters - enough to keep Avrdude happy
|
|
* other parameters - enough to keep Avrdude happy
|
|
*/
|
|
*/
|
|
putch(0x03);
|
|
putch(0x03);
|
|
- 1fc76: 83 e0 ldi r24, 0x03 ; 3
|
|
|
|
- 1fc78: ab d0 rcall .+342 ; 0x1fdd0 <putch>
|
|
|
|
- 1fc7a: a7 c0 rjmp .+334 ; 0x1fdca <main+0x1ca>
|
|
|
|
|
|
+ 1fc7e: 83 e0 ldi r24, 0x03 ; 3
|
|
|
|
+ 1fc80: ab d0 rcall .+342 ; 0x1fdd8 <putch>
|
|
|
|
+ 1fc82: a7 c0 rjmp .+334 ; 0x1fdd2 <main+0x1d2>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
else if(ch == STK_SET_DEVICE) {
|
|
else if(ch == STK_SET_DEVICE) {
|
|
- 1fc7c: 82 34 cpi r24, 0x42 ; 66
|
|
|
|
- 1fc7e: 11 f4 brne .+4 ; 0x1fc84 <main+0x84>
|
|
|
|
|
|
+ 1fc84: 82 34 cpi r24, 0x42 ; 66
|
|
|
|
+ 1fc86: 11 f4 brne .+4 ; 0x1fc8c <main+0x8c>
|
|
// SET DEVICE is ignored
|
|
// SET DEVICE is ignored
|
|
getNch(20);
|
|
getNch(20);
|
|
- 1fc80: 84 e1 ldi r24, 0x14 ; 20
|
|
|
|
- 1fc82: 03 c0 rjmp .+6 ; 0x1fc8a <main+0x8a>
|
|
|
|
|
|
+ 1fc88: 84 e1 ldi r24, 0x14 ; 20
|
|
|
|
+ 1fc8a: 03 c0 rjmp .+6 ; 0x1fc92 <main+0x92>
|
|
}
|
|
}
|
|
else if(ch == STK_SET_DEVICE_EXT) {
|
|
else if(ch == STK_SET_DEVICE_EXT) {
|
|
- 1fc84: 85 34 cpi r24, 0x45 ; 69
|
|
|
|
- 1fc86: 19 f4 brne .+6 ; 0x1fc8e <main+0x8e>
|
|
|
|
|
|
+ 1fc8c: 85 34 cpi r24, 0x45 ; 69
|
|
|
|
+ 1fc8e: 19 f4 brne .+6 ; 0x1fc96 <main+0x96>
|
|
// SET DEVICE EXT is ignored
|
|
// SET DEVICE EXT is ignored
|
|
getNch(5);
|
|
getNch(5);
|
|
- 1fc88: 85 e0 ldi r24, 0x05 ; 5
|
|
|
|
- 1fc8a: c4 d0 rcall .+392 ; 0x1fe14 <getNch>
|
|
|
|
- 1fc8c: 9e c0 rjmp .+316 ; 0x1fdca <main+0x1ca>
|
|
|
|
|
|
+ 1fc90: 85 e0 ldi r24, 0x05 ; 5
|
|
|
|
+ 1fc92: c4 d0 rcall .+392 ; 0x1fe1c <getNch>
|
|
|
|
+ 1fc94: 9e c0 rjmp .+316 ; 0x1fdd2 <main+0x1d2>
|
|
}
|
|
}
|
|
else if(ch == STK_LOAD_ADDRESS) {
|
|
else if(ch == STK_LOAD_ADDRESS) {
|
|
- 1fc8e: 85 35 cpi r24, 0x55 ; 85
|
|
|
|
- 1fc90: a1 f4 brne .+40 ; 0x1fcba <main+0xba>
|
|
|
|
|
|
+ 1fc96: 85 35 cpi r24, 0x55 ; 85
|
|
|
|
+ 1fc98: a1 f4 brne .+40 ; 0x1fcc2 <main+0xc2>
|
|
// LOAD ADDRESS
|
|
// LOAD ADDRESS
|
|
uint16_t newAddress;
|
|
uint16_t newAddress;
|
|
newAddress = getch();
|
|
newAddress = getch();
|
|
- 1fc92: a6 d0 rcall .+332 ; 0x1fde0 <getch>
|
|
|
|
|
|
+ 1fc9a: a6 d0 rcall .+332 ; 0x1fde8 <getch>
|
|
newAddress = (newAddress & 0xff) | (getch() << 8);
|
|
newAddress = (newAddress & 0xff) | (getch() << 8);
|
|
- 1fc94: 08 2f mov r16, r24
|
|
|
|
- 1fc96: 10 e0 ldi r17, 0x00 ; 0
|
|
|
|
- 1fc98: a3 d0 rcall .+326 ; 0x1fde0 <getch>
|
|
|
|
- 1fc9a: e8 2e mov r14, r24
|
|
|
|
- 1fc9c: ff 24 eor r15, r15
|
|
|
|
- 1fc9e: fe 2c mov r15, r14
|
|
|
|
- 1fca0: ee 24 eor r14, r14
|
|
|
|
- 1fca2: e0 2a or r14, r16
|
|
|
|
- 1fca4: f1 2a or r15, r17
|
|
|
|
|
|
+ 1fc9c: 08 2f mov r16, r24
|
|
|
|
+ 1fc9e: 10 e0 ldi r17, 0x00 ; 0
|
|
|
|
+ 1fca0: a3 d0 rcall .+326 ; 0x1fde8 <getch>
|
|
|
|
+ 1fca2: e8 2e mov r14, r24
|
|
|
|
+ 1fca4: ff 24 eor r15, r15
|
|
|
|
+ 1fca6: fe 2c mov r15, r14
|
|
|
|
+ 1fca8: ee 24 eor r14, r14
|
|
|
|
+ 1fcaa: e0 2a or r14, r16
|
|
|
|
+ 1fcac: f1 2a or r15, r17
|
|
#ifdef RAMPZ
|
|
#ifdef RAMPZ
|
|
// Transfer top bit to RAMPZ
|
|
// Transfer top bit to RAMPZ
|
|
RAMPZ = (newAddress & 0x8000) ? 1 : 0;
|
|
RAMPZ = (newAddress & 0x8000) ? 1 : 0;
|
|
- 1fca6: 8f 2d mov r24, r15
|
|
|
|
- 1fca8: 88 1f adc r24, r24
|
|
|
|
- 1fcaa: 88 27 eor r24, r24
|
|
|
|
- 1fcac: 88 1f adc r24, r24
|
|
|
|
- 1fcae: 8b bf out 0x3b, r24 ; 59
|
|
|
|
|
|
+ 1fcae: 8f 2d mov r24, r15
|
|
|
|
+ 1fcb0: 88 1f adc r24, r24
|
|
|
|
+ 1fcb2: 88 27 eor r24, r24
|
|
|
|
+ 1fcb4: 88 1f adc r24, r24
|
|
|
|
+ 1fcb6: 8b bf out 0x3b, r24 ; 59
|
|
#endif
|
|
#endif
|
|
newAddress += newAddress; // Convert from word address to byte address
|
|
newAddress += newAddress; // Convert from word address to byte address
|
|
- 1fcb0: ee 0c add r14, r14
|
|
|
|
- 1fcb2: ff 1c adc r15, r15
|
|
|
|
|
|
+ 1fcb8: ee 0c add r14, r14
|
|
|
|
+ 1fcba: ff 1c adc r15, r15
|
|
address = newAddress;
|
|
address = newAddress;
|
|
verifySpace();
|
|
verifySpace();
|
|
- 1fcb4: a7 d0 rcall .+334 ; 0x1fe04 <verifySpace>
|
|
|
|
- 1fcb6: 67 01 movw r12, r14
|
|
|
|
- 1fcb8: 88 c0 rjmp .+272 ; 0x1fdca <main+0x1ca>
|
|
|
|
|
|
+ 1fcbc: a7 d0 rcall .+334 ; 0x1fe0c <verifySpace>
|
|
|
|
+ 1fcbe: 67 01 movw r12, r14
|
|
|
|
+ 1fcc0: 88 c0 rjmp .+272 ; 0x1fdd2 <main+0x1d2>
|
|
}
|
|
}
|
|
else if(ch == STK_UNIVERSAL) {
|
|
else if(ch == STK_UNIVERSAL) {
|
|
- 1fcba: 86 35 cpi r24, 0x56 ; 86
|
|
|
|
- 1fcbc: 21 f4 brne .+8 ; 0x1fcc6 <main+0xc6>
|
|
|
|
|
|
+ 1fcc2: 86 35 cpi r24, 0x56 ; 86
|
|
|
|
+ 1fcc4: 21 f4 brne .+8 ; 0x1fcce <main+0xce>
|
|
// UNIVERSAL command is ignored
|
|
// UNIVERSAL command is ignored
|
|
getNch(4);
|
|
getNch(4);
|
|
- 1fcbe: 84 e0 ldi r24, 0x04 ; 4
|
|
|
|
- 1fcc0: a9 d0 rcall .+338 ; 0x1fe14 <getNch>
|
|
|
|
|
|
+ 1fcc6: 84 e0 ldi r24, 0x04 ; 4
|
|
|
|
+ 1fcc8: a9 d0 rcall .+338 ; 0x1fe1c <getNch>
|
|
putch(0x00);
|
|
putch(0x00);
|
|
- 1fcc2: 80 e0 ldi r24, 0x00 ; 0
|
|
|
|
- 1fcc4: d9 cf rjmp .-78 ; 0x1fc78 <main+0x78>
|
|
|
|
|
|
+ 1fcca: 80 e0 ldi r24, 0x00 ; 0
|
|
|
|
+ 1fccc: d9 cf rjmp .-78 ; 0x1fc80 <main+0x80>
|
|
}
|
|
}
|
|
/* Write memory, length is big endian and is in bytes */
|
|
/* Write memory, length is big endian and is in bytes */
|
|
else if(ch == STK_PROG_PAGE) {
|
|
else if(ch == STK_PROG_PAGE) {
|
|
- 1fcc6: 84 36 cpi r24, 0x64 ; 100
|
|
|
|
- 1fcc8: 09 f0 breq .+2 ; 0x1fccc <main+0xcc>
|
|
|
|
- 1fcca: 52 c0 rjmp .+164 ; 0x1fd70 <main+0x170>
|
|
|
|
|
|
+ 1fcce: 84 36 cpi r24, 0x64 ; 100
|
|
|
|
+ 1fcd0: 09 f0 breq .+2 ; 0x1fcd4 <main+0xd4>
|
|
|
|
+ 1fcd2: 52 c0 rjmp .+164 ; 0x1fd78 <main+0x178>
|
|
// PROGRAM PAGE - we support flash programming only, not EEPROM
|
|
// PROGRAM PAGE - we support flash programming only, not EEPROM
|
|
uint8_t desttype;
|
|
uint8_t desttype;
|
|
uint8_t *bufPtr;
|
|
uint8_t *bufPtr;
|
|
uint16_t savelength;
|
|
uint16_t savelength;
|
|
|
|
|
|
length = getch()<<8; /* getlen() */
|
|
length = getch()<<8; /* getlen() */
|
|
- 1fccc: 89 d0 rcall .+274 ; 0x1fde0 <getch>
|
|
|
|
- 1fcce: 90 e0 ldi r25, 0x00 ; 0
|
|
|
|
- 1fcd0: 18 2f mov r17, r24
|
|
|
|
- 1fcd2: 00 27 eor r16, r16
|
|
|
|
- length |= getch();
|
|
|
|
- 1fcd4: 85 d0 rcall .+266 ; 0x1fde0 <getch>
|
|
|
|
|
|
+ 1fcd4: 89 d0 rcall .+274 ; 0x1fde8 <getch>
|
|
1fcd6: 90 e0 ldi r25, 0x00 ; 0
|
|
1fcd6: 90 e0 ldi r25, 0x00 ; 0
|
|
- 1fcd8: 08 2b or r16, r24
|
|
|
|
- 1fcda: 19 2b or r17, r25
|
|
|
|
|
|
+ 1fcd8: 18 2f mov r17, r24
|
|
|
|
+ 1fcda: 00 27 eor r16, r16
|
|
|
|
+ length |= getch();
|
|
|
|
+ 1fcdc: 85 d0 rcall .+266 ; 0x1fde8 <getch>
|
|
|
|
+ 1fcde: 90 e0 ldi r25, 0x00 ; 0
|
|
|
|
+ 1fce0: 08 2b or r16, r24
|
|
|
|
+ 1fce2: 19 2b or r17, r25
|
|
savelength = length;
|
|
savelength = length;
|
|
desttype = getch();
|
|
desttype = getch();
|
|
- 1fcdc: 81 d0 rcall .+258 ; 0x1fde0 <getch>
|
|
|
|
- 1fcde: b8 2e mov r11, r24
|
|
|
|
- 1fce0: e8 01 movw r28, r16
|
|
|
|
- 1fce2: e1 2c mov r14, r1
|
|
|
|
- 1fce4: a2 e0 ldi r26, 0x02 ; 2
|
|
|
|
- 1fce6: fa 2e mov r15, r26
|
|
|
|
|
|
+ 1fce4: 81 d0 rcall .+258 ; 0x1fde8 <getch>
|
|
|
|
+ 1fce6: b8 2e mov r11, r24
|
|
|
|
+ 1fce8: e8 01 movw r28, r16
|
|
|
|
+ 1fcea: e1 2c mov r14, r1
|
|
|
|
+ 1fcec: a2 e0 ldi r26, 0x02 ; 2
|
|
|
|
+ 1fcee: fa 2e mov r15, r26
|
|
|
|
|
|
// read a page worth of contents
|
|
// read a page worth of contents
|
|
bufPtr = buff;
|
|
bufPtr = buff;
|
|
do *bufPtr++ = getch();
|
|
do *bufPtr++ = getch();
|
|
- 1fce8: 7b d0 rcall .+246 ; 0x1fde0 <getch>
|
|
|
|
- 1fcea: f7 01 movw r30, r14
|
|
|
|
- 1fcec: 81 93 st Z+, r24
|
|
|
|
- 1fcee: 7f 01 movw r14, r30
|
|
|
|
|
|
+ 1fcf0: 7b d0 rcall .+246 ; 0x1fde8 <getch>
|
|
|
|
+ 1fcf2: f7 01 movw r30, r14
|
|
|
|
+ 1fcf4: 81 93 st Z+, r24
|
|
|
|
+ 1fcf6: 7f 01 movw r14, r30
|
|
while (--length);
|
|
while (--length);
|
|
- 1fcf0: 21 97 sbiw r28, 0x01 ; 1
|
|
|
|
- 1fcf2: d1 f7 brne .-12 ; 0x1fce8 <main+0xe8>
|
|
|
|
|
|
+ 1fcf8: 21 97 sbiw r28, 0x01 ; 1
|
|
|
|
+ 1fcfa: d1 f7 brne .-12 ; 0x1fcf0 <main+0xf0>
|
|
|
|
|
|
// Read command terminator, start reply
|
|
// Read command terminator, start reply
|
|
verifySpace();
|
|
verifySpace();
|
|
- 1fcf4: 87 d0 rcall .+270 ; 0x1fe04 <verifySpace>
|
|
|
|
|
|
+ 1fcfc: 87 d0 rcall .+270 ; 0x1fe0c <verifySpace>
|
|
* void writebuffer(memtype, buffer, address, length)
|
|
* void writebuffer(memtype, buffer, address, length)
|
|
*/
|
|
*/
|
|
static inline void writebuffer(int8_t memtype, uint8_t *mybuff,
|
|
static inline void writebuffer(int8_t memtype, uint8_t *mybuff,
|
|
uint16_t address, uint16_t len)
|
|
uint16_t address, uint16_t len)
|
|
{
|
|
{
|
|
switch (memtype) {
|
|
switch (memtype) {
|
|
- 1fcf6: f5 e4 ldi r31, 0x45 ; 69
|
|
|
|
- 1fcf8: bf 16 cp r11, r31
|
|
|
|
- 1fcfa: 89 f4 brne .+34 ; 0x1fd1e <main+0x11e>
|
|
|
|
- 1fcfc: e6 01 movw r28, r12
|
|
|
|
- 1fcfe: e1 2c mov r14, r1
|
|
|
|
- 1fd00: f2 e0 ldi r31, 0x02 ; 2
|
|
|
|
- 1fd02: ff 2e mov r15, r31
|
|
|
|
- 1fd04: 08 c0 rjmp .+16 ; 0x1fd16 <main+0x116>
|
|
|
|
- 1fd06: ce 01 movw r24, r28
|
|
|
|
|
|
+ 1fcfe: f5 e4 ldi r31, 0x45 ; 69
|
|
|
|
+ 1fd00: bf 16 cp r11, r31
|
|
|
|
+ 1fd02: 89 f4 brne .+34 ; 0x1fd26 <main+0x126>
|
|
|
|
+ 1fd04: e6 01 movw r28, r12
|
|
|
|
+ 1fd06: e1 2c mov r14, r1
|
|
|
|
+ 1fd08: f2 e0 ldi r31, 0x02 ; 2
|
|
|
|
+ 1fd0a: ff 2e mov r15, r31
|
|
|
|
+ 1fd0c: 08 c0 rjmp .+16 ; 0x1fd1e <main+0x11e>
|
|
|
|
+ 1fd0e: ce 01 movw r24, r28
|
|
case 'E': // EEPROM
|
|
case 'E': // EEPROM
|
|
#if defined(SUPPORT_EEPROM) || defined(BIGBOOT)
|
|
#if defined(SUPPORT_EEPROM) || defined(BIGBOOT)
|
|
while(len--) {
|
|
while(len--) {
|
|
eeprom_write_byte((uint8_t *)(address++), *mybuff++);
|
|
eeprom_write_byte((uint8_t *)(address++), *mybuff++);
|
|
- 1fd08: 21 96 adiw r28, 0x01 ; 1
|
|
|
|
- 1fd0a: f7 01 movw r30, r14
|
|
|
|
- 1fd0c: 61 91 ld r22, Z+
|
|
|
|
- 1fd0e: 7f 01 movw r14, r30
|
|
|
|
- 1fd10: 97 d0 rcall .+302 ; 0x1fe40 <__eewr_byte_m1280>
|
|
|
|
- 1fd12: 01 50 subi r16, 0x01 ; 1
|
|
|
|
- 1fd14: 10 40 sbci r17, 0x00 ; 0
|
|
|
|
|
|
+ 1fd10: 21 96 adiw r28, 0x01 ; 1
|
|
|
|
+ 1fd12: f7 01 movw r30, r14
|
|
|
|
+ 1fd14: 61 91 ld r22, Z+
|
|
|
|
+ 1fd16: 7f 01 movw r14, r30
|
|
|
|
+ 1fd18: 97 d0 rcall .+302 ; 0x1fe48 <__eewr_byte_m1280>
|
|
|
|
+ 1fd1a: 01 50 subi r16, 0x01 ; 1
|
|
|
|
+ 1fd1c: 10 40 sbci r17, 0x00 ; 0
|
|
uint16_t address, uint16_t len)
|
|
uint16_t address, uint16_t len)
|
|
{
|
|
{
|
|
switch (memtype) {
|
|
switch (memtype) {
|
|
case 'E': // EEPROM
|
|
case 'E': // EEPROM
|
|
#if defined(SUPPORT_EEPROM) || defined(BIGBOOT)
|
|
#if defined(SUPPORT_EEPROM) || defined(BIGBOOT)
|
|
while(len--) {
|
|
while(len--) {
|
|
- 1fd16: 01 15 cp r16, r1
|
|
|
|
- 1fd18: 11 05 cpc r17, r1
|
|
|
|
- 1fd1a: a9 f7 brne .-22 ; 0x1fd06 <main+0x106>
|
|
|
|
- 1fd1c: 56 c0 rjmp .+172 ; 0x1fdca <main+0x1ca>
|
|
|
|
|
|
+ 1fd1e: 01 15 cp r16, r1
|
|
|
|
+ 1fd20: 11 05 cpc r17, r1
|
|
|
|
+ 1fd22: a9 f7 brne .-22 ; 0x1fd0e <main+0x10e>
|
|
|
|
+ 1fd24: 56 c0 rjmp .+172 ; 0x1fdd2 <main+0x1d2>
|
|
* Start the page erase and wait for it to finish. There
|
|
* Start the page erase and wait for it to finish. There
|
|
* used to be code to do this while receiving the data over
|
|
* used to be code to do this while receiving the data over
|
|
* the serial link, but the performance improvement was slight,
|
|
* the serial link, but the performance improvement was slight,
|
|
* and we needed the space back.
|
|
* and we needed the space back.
|
|
*/
|
|
*/
|
|
__boot_page_erase_short((uint16_t)(void*)address);
|
|
__boot_page_erase_short((uint16_t)(void*)address);
|
|
- 1fd1e: 83 e0 ldi r24, 0x03 ; 3
|
|
|
|
- 1fd20: f6 01 movw r30, r12
|
|
|
|
- 1fd22: 87 bf out 0x37, r24 ; 55
|
|
|
|
- 1fd24: e8 95 spm
|
|
|
|
|
|
+ 1fd26: 83 e0 ldi r24, 0x03 ; 3
|
|
|
|
+ 1fd28: f6 01 movw r30, r12
|
|
|
|
+ 1fd2a: 87 bf out 0x37, r24 ; 55
|
|
|
|
+ 1fd2c: e8 95 spm
|
|
boot_spm_busy_wait();
|
|
boot_spm_busy_wait();
|
|
- 1fd26: 07 b6 in r0, 0x37 ; 55
|
|
|
|
- 1fd28: 00 fc sbrc r0, 0
|
|
|
|
- 1fd2a: fd cf rjmp .-6 ; 0x1fd26 <main+0x126>
|
|
|
|
- 1fd2c: b8 01 movw r22, r16
|
|
|
|
- 1fd2e: a6 01 movw r20, r12
|
|
|
|
- 1fd30: a0 e0 ldi r26, 0x00 ; 0
|
|
|
|
- 1fd32: b2 e0 ldi r27, 0x02 ; 2
|
|
|
|
|
|
+ 1fd2e: 07 b6 in r0, 0x37 ; 55
|
|
|
|
+ 1fd30: 00 fc sbrc r0, 0
|
|
|
|
+ 1fd32: fd cf rjmp .-6 ; 0x1fd2e <main+0x12e>
|
|
|
|
+ 1fd34: b8 01 movw r22, r16
|
|
|
|
+ 1fd36: a6 01 movw r20, r12
|
|
|
|
+ 1fd38: a0 e0 ldi r26, 0x00 ; 0
|
|
|
|
+ 1fd3a: b2 e0 ldi r27, 0x02 ; 2
|
|
/*
|
|
/*
|
|
* Copy data from the buffer into the flash write buffer.
|
|
* Copy data from the buffer into the flash write buffer.
|
|
*/
|
|
*/
|
|
do {
|
|
do {
|
|
uint16_t a;
|
|
uint16_t a;
|
|
a = *bufPtr++;
|
|
a = *bufPtr++;
|
|
- 1fd34: 2c 91 ld r18, X
|
|
|
|
- 1fd36: 30 e0 ldi r19, 0x00 ; 0
|
|
|
|
|
|
+ 1fd3c: 2c 91 ld r18, X
|
|
|
|
+ 1fd3e: 30 e0 ldi r19, 0x00 ; 0
|
|
a |= (*bufPtr++) << 8;
|
|
a |= (*bufPtr++) << 8;
|
|
- 1fd38: 11 96 adiw r26, 0x01 ; 1
|
|
|
|
- 1fd3a: 8c 91 ld r24, X
|
|
|
|
- 1fd3c: 11 97 sbiw r26, 0x01 ; 1
|
|
|
|
- 1fd3e: 90 e0 ldi r25, 0x00 ; 0
|
|
|
|
- 1fd40: 98 2f mov r25, r24
|
|
|
|
- 1fd42: 88 27 eor r24, r24
|
|
|
|
- 1fd44: 82 2b or r24, r18
|
|
|
|
- 1fd46: 93 2b or r25, r19
|
|
|
|
|
|
+ 1fd40: 11 96 adiw r26, 0x01 ; 1
|
|
|
|
+ 1fd42: 8c 91 ld r24, X
|
|
|
|
+ 1fd44: 11 97 sbiw r26, 0x01 ; 1
|
|
|
|
+ 1fd46: 90 e0 ldi r25, 0x00 ; 0
|
|
|
|
+ 1fd48: 98 2f mov r25, r24
|
|
|
|
+ 1fd4a: 88 27 eor r24, r24
|
|
|
|
+ 1fd4c: 82 2b or r24, r18
|
|
|
|
+ 1fd4e: 93 2b or r25, r19
|
|
#define wdtVect (*(uint16_t*)(RAMSTART+SPM_PAGESIZE*2+6))
|
|
#define wdtVect (*(uint16_t*)(RAMSTART+SPM_PAGESIZE*2+6))
|
|
#endif
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/* main program starts here */
|
|
/* main program starts here */
|
|
int main(void) {
|
|
int main(void) {
|
|
- 1fd48: 12 96 adiw r26, 0x02 ; 2
|
|
|
|
|
|
+ 1fd50: 12 96 adiw r26, 0x02 ; 2
|
|
*/
|
|
*/
|
|
do {
|
|
do {
|
|
uint16_t a;
|
|
uint16_t a;
|
|
a = *bufPtr++;
|
|
a = *bufPtr++;
|
|
a |= (*bufPtr++) << 8;
|
|
a |= (*bufPtr++) << 8;
|
|
__boot_page_fill_short((uint16_t)(void*)addrPtr,a);
|
|
__boot_page_fill_short((uint16_t)(void*)addrPtr,a);
|
|
- 1fd4a: fa 01 movw r30, r20
|
|
|
|
- 1fd4c: 0c 01 movw r0, r24
|
|
|
|
- 1fd4e: 87 be out 0x37, r8 ; 55
|
|
|
|
- 1fd50: e8 95 spm
|
|
|
|
- 1fd52: 11 24 eor r1, r1
|
|
|
|
|
|
+ 1fd52: fa 01 movw r30, r20
|
|
|
|
+ 1fd54: 0c 01 movw r0, r24
|
|
|
|
+ 1fd56: 87 be out 0x37, r8 ; 55
|
|
|
|
+ 1fd58: e8 95 spm
|
|
|
|
+ 1fd5a: 11 24 eor r1, r1
|
|
addrPtr += 2;
|
|
addrPtr += 2;
|
|
- 1fd54: 4e 5f subi r20, 0xFE ; 254
|
|
|
|
- 1fd56: 5f 4f sbci r21, 0xFF ; 255
|
|
|
|
|
|
+ 1fd5c: 4e 5f subi r20, 0xFE ; 254
|
|
|
|
+ 1fd5e: 5f 4f sbci r21, 0xFF ; 255
|
|
} while (len -= 2);
|
|
} while (len -= 2);
|
|
- 1fd58: 62 50 subi r22, 0x02 ; 2
|
|
|
|
- 1fd5a: 70 40 sbci r23, 0x00 ; 0
|
|
|
|
- 1fd5c: 59 f7 brne .-42 ; 0x1fd34 <main+0x134>
|
|
|
|
|
|
+ 1fd60: 62 50 subi r22, 0x02 ; 2
|
|
|
|
+ 1fd62: 70 40 sbci r23, 0x00 ; 0
|
|
|
|
+ 1fd64: 59 f7 brne .-42 ; 0x1fd3c <main+0x13c>
|
|
|
|
|
|
/*
|
|
/*
|
|
* Actually Write the buffer to flash (and wait for it to finish.)
|
|
* Actually Write the buffer to flash (and wait for it to finish.)
|
|
*/
|
|
*/
|
|
__boot_page_write_short((uint16_t)(void*)address);
|
|
__boot_page_write_short((uint16_t)(void*)address);
|
|
- 1fd5e: f6 01 movw r30, r12
|
|
|
|
- 1fd60: a7 be out 0x37, r10 ; 55
|
|
|
|
- 1fd62: e8 95 spm
|
|
|
|
|
|
+ 1fd66: f6 01 movw r30, r12
|
|
|
|
+ 1fd68: a7 be out 0x37, r10 ; 55
|
|
|
|
+ 1fd6a: e8 95 spm
|
|
boot_spm_busy_wait();
|
|
boot_spm_busy_wait();
|
|
- 1fd64: 07 b6 in r0, 0x37 ; 55
|
|
|
|
- 1fd66: 00 fc sbrc r0, 0
|
|
|
|
- 1fd68: fd cf rjmp .-6 ; 0x1fd64 <main+0x164>
|
|
|
|
|
|
+ 1fd6c: 07 b6 in r0, 0x37 ; 55
|
|
|
|
+ 1fd6e: 00 fc sbrc r0, 0
|
|
|
|
+ 1fd70: fd cf rjmp .-6 ; 0x1fd6c <main+0x16c>
|
|
#if defined(RWWSRE)
|
|
#if defined(RWWSRE)
|
|
// Reenable read access to flash
|
|
// Reenable read access to flash
|
|
boot_rww_enable();
|
|
boot_rww_enable();
|
|
- 1fd6a: 97 be out 0x37, r9 ; 55
|
|
|
|
- 1fd6c: e8 95 spm
|
|
|
|
- 1fd6e: 2d c0 rjmp .+90 ; 0x1fdca <main+0x1ca>
|
|
|
|
|
|
+ 1fd72: 97 be out 0x37, r9 ; 55
|
|
|
|
+ 1fd74: e8 95 spm
|
|
|
|
+ 1fd76: 2d c0 rjmp .+90 ; 0x1fdd2 <main+0x1d2>
|
|
writebuffer(desttype, buff, address, savelength);
|
|
writebuffer(desttype, buff, address, savelength);
|
|
|
|
|
|
|
|
|
|
}
|
|
}
|
|
/* Read memory block mode, length is big endian. */
|
|
/* Read memory block mode, length is big endian. */
|
|
else if(ch == STK_READ_PAGE) {
|
|
else if(ch == STK_READ_PAGE) {
|
|
- 1fd70: 84 37 cpi r24, 0x74 ; 116
|
|
|
|
- 1fd72: f1 f4 brne .+60 ; 0x1fdb0 <main+0x1b0>
|
|
|
|
|
|
+ 1fd78: 84 37 cpi r24, 0x74 ; 116
|
|
|
|
+ 1fd7a: f1 f4 brne .+60 ; 0x1fdb8 <main+0x1b8>
|
|
uint8_t desttype;
|
|
uint8_t desttype;
|
|
length = getch()<<8; /* getlen() */
|
|
length = getch()<<8; /* getlen() */
|
|
- 1fd74: 35 d0 rcall .+106 ; 0x1fde0 <getch>
|
|
|
|
- 1fd76: 90 e0 ldi r25, 0x00 ; 0
|
|
|
|
- 1fd78: d8 2f mov r29, r24
|
|
|
|
- 1fd7a: cc 27 eor r28, r28
|
|
|
|
- length |= getch();
|
|
|
|
- 1fd7c: 31 d0 rcall .+98 ; 0x1fde0 <getch>
|
|
|
|
|
|
+ 1fd7c: 35 d0 rcall .+106 ; 0x1fde8 <getch>
|
|
1fd7e: 90 e0 ldi r25, 0x00 ; 0
|
|
1fd7e: 90 e0 ldi r25, 0x00 ; 0
|
|
- 1fd80: c8 2b or r28, r24
|
|
|
|
- 1fd82: d9 2b or r29, r25
|
|
|
|
|
|
+ 1fd80: d8 2f mov r29, r24
|
|
|
|
+ 1fd82: cc 27 eor r28, r28
|
|
|
|
+ length |= getch();
|
|
|
|
+ 1fd84: 31 d0 rcall .+98 ; 0x1fde8 <getch>
|
|
|
|
+ 1fd86: 90 e0 ldi r25, 0x00 ; 0
|
|
|
|
+ 1fd88: c8 2b or r28, r24
|
|
|
|
+ 1fd8a: d9 2b or r29, r25
|
|
desttype = getch();
|
|
desttype = getch();
|
|
- 1fd84: 2d d0 rcall .+90 ; 0x1fde0 <getch>
|
|
|
|
- 1fd86: 18 2f mov r17, r24
|
|
|
|
|
|
+ 1fd8c: 2d d0 rcall .+90 ; 0x1fde8 <getch>
|
|
|
|
+ 1fd8e: 18 2f mov r17, r24
|
|
|
|
|
|
verifySpace();
|
|
verifySpace();
|
|
- 1fd88: 3d d0 rcall .+122 ; 0x1fe04 <verifySpace>
|
|
|
|
|
|
+ 1fd90: 3d d0 rcall .+122 ; 0x1fe0c <verifySpace>
|
|
|
|
|
|
static inline void read_mem(uint8_t memtype, uint16_t address, uint16_t length)
|
|
static inline void read_mem(uint8_t memtype, uint16_t address, uint16_t length)
|
|
{
|
|
{
|
|
uint8_t ch;
|
|
uint8_t ch;
|
|
|
|
|
|
switch (memtype) {
|
|
switch (memtype) {
|
|
- 1fd8a: 15 34 cpi r17, 0x45 ; 69
|
|
|
|
- 1fd8c: 49 f4 brne .+18 ; 0x1fda0 <main+0x1a0>
|
|
|
|
- 1fd8e: 86 01 movw r16, r12
|
|
|
|
- 1fd90: c8 01 movw r24, r16
|
|
|
|
|
|
+ 1fd92: 15 34 cpi r17, 0x45 ; 69
|
|
|
|
+ 1fd94: 49 f4 brne .+18 ; 0x1fda8 <main+0x1a8>
|
|
|
|
+ 1fd96: 86 01 movw r16, r12
|
|
|
|
+ 1fd98: c8 01 movw r24, r16
|
|
|
|
|
|
#if defined(SUPPORT_EEPROM) || defined(BIGBOOT)
|
|
#if defined(SUPPORT_EEPROM) || defined(BIGBOOT)
|
|
case 'E': // EEPROM
|
|
case 'E': // EEPROM
|
|
do {
|
|
do {
|
|
putch(eeprom_read_byte((uint8_t *)(address++)));
|
|
putch(eeprom_read_byte((uint8_t *)(address++)));
|
|
- 1fd92: 0f 5f subi r16, 0xFF ; 255
|
|
|
|
- 1fd94: 1f 4f sbci r17, 0xFF ; 255
|
|
|
|
- 1fd96: 4c d0 rcall .+152 ; 0x1fe30 <__eerd_byte_m1280>
|
|
|
|
- 1fd98: 1b d0 rcall .+54 ; 0x1fdd0 <putch>
|
|
|
|
|
|
+ 1fd9a: 0f 5f subi r16, 0xFF ; 255
|
|
|
|
+ 1fd9c: 1f 4f sbci r17, 0xFF ; 255
|
|
|
|
+ 1fd9e: 4c d0 rcall .+152 ; 0x1fe38 <__eerd_byte_m1280>
|
|
|
|
+ 1fda0: 1b d0 rcall .+54 ; 0x1fdd8 <putch>
|
|
} while (--length);
|
|
} while (--length);
|
|
- 1fd9a: 21 97 sbiw r28, 0x01 ; 1
|
|
|
|
- 1fd9c: c9 f7 brne .-14 ; 0x1fd90 <main+0x190>
|
|
|
|
- 1fd9e: 15 c0 rjmp .+42 ; 0x1fdca <main+0x1ca>
|
|
|
|
- 1fda0: 86 01 movw r16, r12
|
|
|
|
|
|
+ 1fda2: 21 97 sbiw r28, 0x01 ; 1
|
|
|
|
+ 1fda4: c9 f7 brne .-14 ; 0x1fd98 <main+0x198>
|
|
|
|
+ 1fda6: 15 c0 rjmp .+42 ; 0x1fdd2 <main+0x1d2>
|
|
|
|
+ 1fda8: 86 01 movw r16, r12
|
|
__asm__ ("elpm %0,Z+\n" : "=r" (ch), "=z" (address): "1" (address));
|
|
__asm__ ("elpm %0,Z+\n" : "=r" (ch), "=z" (address): "1" (address));
|
|
#else
|
|
#else
|
|
// read a Flash byte and increment the address
|
|
// read a Flash byte and increment the address
|
|
__asm__ ("lpm %0,Z+\n" : "=r" (ch), "=z" (address): "1" (address));
|
|
__asm__ ("lpm %0,Z+\n" : "=r" (ch), "=z" (address): "1" (address));
|
|
#endif
|
|
#endif
|
|
putch(ch);
|
|
putch(ch);
|
|
- 1fda2: f8 01 movw r30, r16
|
|
|
|
- 1fda4: 87 91 elpm r24, Z+
|
|
|
|
- 1fda6: 8f 01 movw r16, r30
|
|
|
|
- 1fda8: 13 d0 rcall .+38 ; 0x1fdd0 <putch>
|
|
|
|
|
|
+ 1fdaa: f8 01 movw r30, r16
|
|
|
|
+ 1fdac: 87 91 elpm r24, Z+
|
|
|
|
+ 1fdae: 8f 01 movw r16, r30
|
|
|
|
+ 1fdb0: 13 d0 rcall .+38 ; 0x1fdd8 <putch>
|
|
} while (--length);
|
|
} while (--length);
|
|
- 1fdaa: 21 97 sbiw r28, 0x01 ; 1
|
|
|
|
- 1fdac: d1 f7 brne .-12 ; 0x1fda2 <main+0x1a2>
|
|
|
|
- 1fdae: 0d c0 rjmp .+26 ; 0x1fdca <main+0x1ca>
|
|
|
|
|
|
+ 1fdb2: 21 97 sbiw r28, 0x01 ; 1
|
|
|
|
+ 1fdb4: d1 f7 brne .-12 ; 0x1fdaa <main+0x1aa>
|
|
|
|
+ 1fdb6: 0d c0 rjmp .+26 ; 0x1fdd2 <main+0x1d2>
|
|
|
|
|
|
read_mem(desttype, address, length);
|
|
read_mem(desttype, address, length);
|
|
}
|
|
}
|
|
|
|
|
|
/* Get device signature bytes */
|
|
/* Get device signature bytes */
|
|
else if(ch == STK_READ_SIGN) {
|
|
else if(ch == STK_READ_SIGN) {
|
|
- 1fdb0: 85 37 cpi r24, 0x75 ; 117
|
|
|
|
- 1fdb2: 31 f4 brne .+12 ; 0x1fdc0 <main+0x1c0>
|
|
|
|
|
|
+ 1fdb8: 85 37 cpi r24, 0x75 ; 117
|
|
|
|
+ 1fdba: 31 f4 brne .+12 ; 0x1fdc8 <main+0x1c8>
|
|
// READ SIGN - return what Avrdude wants to hear
|
|
// READ SIGN - return what Avrdude wants to hear
|
|
verifySpace();
|
|
verifySpace();
|
|
- 1fdb4: 27 d0 rcall .+78 ; 0x1fe04 <verifySpace>
|
|
|
|
|
|
+ 1fdbc: 27 d0 rcall .+78 ; 0x1fe0c <verifySpace>
|
|
putch(SIGNATURE_0);
|
|
putch(SIGNATURE_0);
|
|
- 1fdb6: 8e e1 ldi r24, 0x1E ; 30
|
|
|
|
- 1fdb8: 0b d0 rcall .+22 ; 0x1fdd0 <putch>
|
|
|
|
|
|
+ 1fdbe: 8e e1 ldi r24, 0x1E ; 30
|
|
|
|
+ 1fdc0: 0b d0 rcall .+22 ; 0x1fdd8 <putch>
|
|
putch(SIGNATURE_1);
|
|
putch(SIGNATURE_1);
|
|
- 1fdba: 87 e9 ldi r24, 0x97 ; 151
|
|
|
|
- 1fdbc: 09 d0 rcall .+18 ; 0x1fdd0 <putch>
|
|
|
|
- 1fdbe: 5b cf rjmp .-330 ; 0x1fc76 <main+0x76>
|
|
|
|
|
|
+ 1fdc2: 87 e9 ldi r24, 0x97 ; 151
|
|
|
|
+ 1fdc4: 09 d0 rcall .+18 ; 0x1fdd8 <putch>
|
|
|
|
+ 1fdc6: 5b cf rjmp .-330 ; 0x1fc7e <main+0x7e>
|
|
putch(SIGNATURE_2);
|
|
putch(SIGNATURE_2);
|
|
}
|
|
}
|
|
else if (ch == STK_LEAVE_PROGMODE) { /* 'Q' */
|
|
else if (ch == STK_LEAVE_PROGMODE) { /* 'Q' */
|
|
- 1fdc0: 81 35 cpi r24, 0x51 ; 81
|
|
|
|
- 1fdc2: 11 f4 brne .+4 ; 0x1fdc8 <main+0x1c8>
|
|
|
|
|
|
+ 1fdc8: 81 35 cpi r24, 0x51 ; 81
|
|
|
|
+ 1fdca: 11 f4 brne .+4 ; 0x1fdd0 <main+0x1d0>
|
|
// Adaboot no-wait mod
|
|
// Adaboot no-wait mod
|
|
watchdogConfig(WATCHDOG_16MS);
|
|
watchdogConfig(WATCHDOG_16MS);
|
|
- 1fdc4: 88 e0 ldi r24, 0x08 ; 8
|
|
|
|
- 1fdc6: 18 d0 rcall .+48 ; 0x1fdf8 <watchdogConfig>
|
|
|
|
|
|
+ 1fdcc: 88 e0 ldi r24, 0x08 ; 8
|
|
|
|
+ 1fdce: 18 d0 rcall .+48 ; 0x1fe00 <watchdogConfig>
|
|
verifySpace();
|
|
verifySpace();
|
|
}
|
|
}
|
|
else {
|
|
else {
|
|
// This covers the response to commands like STK_ENTER_PROGMODE
|
|
// This covers the response to commands like STK_ENTER_PROGMODE
|
|
verifySpace();
|
|
verifySpace();
|
|
- 1fdc8: 1d d0 rcall .+58 ; 0x1fe04 <verifySpace>
|
|
|
|
|
|
+ 1fdd0: 1d d0 rcall .+58 ; 0x1fe0c <verifySpace>
|
|
}
|
|
}
|
|
putch(STK_OK);
|
|
putch(STK_OK);
|
|
- 1fdca: 80 e1 ldi r24, 0x10 ; 16
|
|
|
|
- 1fdcc: 01 d0 rcall .+2 ; 0x1fdd0 <putch>
|
|
|
|
- 1fdce: 47 cf rjmp .-370 ; 0x1fc5e <main+0x5e>
|
|
|
|
|
|
+ 1fdd2: 80 e1 ldi r24, 0x10 ; 16
|
|
|
|
+ 1fdd4: 01 d0 rcall .+2 ; 0x1fdd8 <putch>
|
|
|
|
+ 1fdd6: 45 cf rjmp .-374 ; 0x1fc62 <main+0x62>
|
|
|
|
|
|
-0001fdd0 <putch>:
|
|
|
|
|
|
+0001fdd8 <putch>:
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
void putch(char ch) {
|
|
void putch(char ch) {
|
|
- 1fdd0: 98 2f mov r25, r24
|
|
|
|
|
|
+ 1fdd8: 98 2f mov r25, r24
|
|
#ifndef SOFT_UART
|
|
#ifndef SOFT_UART
|
|
while (!(UART_SRA & _BV(UDRE0)));
|
|
while (!(UART_SRA & _BV(UDRE0)));
|
|
- 1fdd2: 80 91 c0 00 lds r24, 0x00C0
|
|
|
|
- 1fdd6: 85 ff sbrs r24, 5
|
|
|
|
- 1fdd8: fc cf rjmp .-8 ; 0x1fdd2 <putch+0x2>
|
|
|
|
|
|
+ 1fdda: 80 91 c0 00 lds r24, 0x00C0
|
|
|
|
+ 1fdde: 85 ff sbrs r24, 5
|
|
|
|
+ 1fde0: fc cf rjmp .-8 ; 0x1fdda <putch+0x2>
|
|
UART_UDR = ch;
|
|
UART_UDR = ch;
|
|
- 1fdda: 90 93 c6 00 sts 0x00C6, r25
|
|
|
|
|
|
+ 1fde2: 90 93 c6 00 sts 0x00C6, r25
|
|
[uartBit] "I" (UART_TX_BIT)
|
|
[uartBit] "I" (UART_TX_BIT)
|
|
:
|
|
:
|
|
"r25"
|
|
"r25"
|
|
);
|
|
);
|
|
#endif
|
|
#endif
|
|
}
|
|
}
|
|
- 1fdde: 08 95 ret
|
|
|
|
|
|
+ 1fde6: 08 95 ret
|
|
|
|
|
|
-0001fde0 <getch>:
|
|
|
|
|
|
+0001fde8 <getch>:
|
|
[uartBit] "I" (UART_RX_BIT)
|
|
[uartBit] "I" (UART_RX_BIT)
|
|
:
|
|
:
|
|
"r25"
|
|
"r25"
|
|
);
|
|
);
|
|
#else
|
|
#else
|
|
while(!(UART_SRA & _BV(RXC0)))
|
|
while(!(UART_SRA & _BV(RXC0)))
|
|
- 1fde0: 80 91 c0 00 lds r24, 0x00C0
|
|
|
|
- 1fde4: 87 ff sbrs r24, 7
|
|
|
|
- 1fde6: fc cf rjmp .-8 ; 0x1fde0 <getch>
|
|
|
|
|
|
+ 1fde8: 80 91 c0 00 lds r24, 0x00C0
|
|
|
|
+ 1fdec: 87 ff sbrs r24, 7
|
|
|
|
+ 1fdee: fc cf rjmp .-8 ; 0x1fde8 <getch>
|
|
;
|
|
;
|
|
if (!(UART_SRA & _BV(FE0))) {
|
|
if (!(UART_SRA & _BV(FE0))) {
|
|
- 1fde8: 80 91 c0 00 lds r24, 0x00C0
|
|
|
|
- 1fdec: 84 fd sbrc r24, 4
|
|
|
|
- 1fdee: 01 c0 rjmp .+2 ; 0x1fdf2 <getch+0x12>
|
|
|
|
|
|
+ 1fdf0: 80 91 c0 00 lds r24, 0x00C0
|
|
|
|
+ 1fdf4: 84 fd sbrc r24, 4
|
|
|
|
+ 1fdf6: 01 c0 rjmp .+2 ; 0x1fdfa <getch+0x12>
|
|
}
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
|
|
// Watchdog functions. These are only safe with interrupts turned off.
|
|
// Watchdog functions. These are only safe with interrupts turned off.
|
|
void watchdogReset() {
|
|
void watchdogReset() {
|
|
__asm__ __volatile__ (
|
|
__asm__ __volatile__ (
|
|
- 1fdf0: a8 95 wdr
|
|
|
|
|
|
+ 1fdf8: a8 95 wdr
|
|
* don't care that an invalid char is returned...)
|
|
* don't care that an invalid char is returned...)
|
|
*/
|
|
*/
|
|
watchdogReset();
|
|
watchdogReset();
|
|
}
|
|
}
|
|
|
|
|
|
ch = UART_UDR;
|
|
ch = UART_UDR;
|
|
- 1fdf2: 80 91 c6 00 lds r24, 0x00C6
|
|
|
|
|
|
+ 1fdfa: 80 91 c6 00 lds r24, 0x00C6
|
|
LED_PIN |= _BV(LED);
|
|
LED_PIN |= _BV(LED);
|
|
#endif
|
|
#endif
|
|
#endif
|
|
#endif
|
|
|
|
|
|
return ch;
|
|
return ch;
|
|
}
|
|
}
|
|
- 1fdf6: 08 95 ret
|
|
|
|
|
|
+ 1fdfe: 08 95 ret
|
|
|
|
|
|
-0001fdf8 <watchdogConfig>:
|
|
|
|
|
|
+0001fe00 <watchdogConfig>:
|
|
"wdr\n"
|
|
"wdr\n"
|
|
);
|
|
);
|
|
}
|
|
}
|
|
|
|
|
|
void watchdogConfig(uint8_t x) {
|
|
void watchdogConfig(uint8_t x) {
|
|
WDTCSR = _BV(WDCE) | _BV(WDE);
|
|
WDTCSR = _BV(WDCE) | _BV(WDE);
|
|
- 1fdf8: e0 e6 ldi r30, 0x60 ; 96
|
|
|
|
- 1fdfa: f0 e0 ldi r31, 0x00 ; 0
|
|
|
|
- 1fdfc: 98 e1 ldi r25, 0x18 ; 24
|
|
|
|
- 1fdfe: 90 83 st Z, r25
|
|
|
|
|
|
+ 1fe00: e0 e6 ldi r30, 0x60 ; 96
|
|
|
|
+ 1fe02: f0 e0 ldi r31, 0x00 ; 0
|
|
|
|
+ 1fe04: 98 e1 ldi r25, 0x18 ; 24
|
|
|
|
+ 1fe06: 90 83 st Z, r25
|
|
WDTCSR = x;
|
|
WDTCSR = x;
|
|
- 1fe00: 80 83 st Z, r24
|
|
|
|
|
|
+ 1fe08: 80 83 st Z, r24
|
|
}
|
|
}
|
|
- 1fe02: 08 95 ret
|
|
|
|
|
|
+ 1fe0a: 08 95 ret
|
|
|
|
|
|
-0001fe04 <verifySpace>:
|
|
|
|
|
|
+0001fe0c <verifySpace>:
|
|
do getch(); while (--count);
|
|
do getch(); while (--count);
|
|
verifySpace();
|
|
verifySpace();
|
|
}
|
|
}
|
|
|
|
|
|
void verifySpace() {
|
|
void verifySpace() {
|
|
if (getch() != CRC_EOP) {
|
|
if (getch() != CRC_EOP) {
|
|
- 1fe04: ed df rcall .-38 ; 0x1fde0 <getch>
|
|
|
|
- 1fe06: 80 32 cpi r24, 0x20 ; 32
|
|
|
|
- 1fe08: 19 f0 breq .+6 ; 0x1fe10 <verifySpace+0xc>
|
|
|
|
|
|
+ 1fe0c: ed df rcall .-38 ; 0x1fde8 <getch>
|
|
|
|
+ 1fe0e: 80 32 cpi r24, 0x20 ; 32
|
|
|
|
+ 1fe10: 19 f0 breq .+6 ; 0x1fe18 <verifySpace+0xc>
|
|
watchdogConfig(WATCHDOG_16MS); // shorten WD timeout
|
|
watchdogConfig(WATCHDOG_16MS); // shorten WD timeout
|
|
- 1fe0a: 88 e0 ldi r24, 0x08 ; 8
|
|
|
|
- 1fe0c: f5 df rcall .-22 ; 0x1fdf8 <watchdogConfig>
|
|
|
|
- 1fe0e: ff cf rjmp .-2 ; 0x1fe0e <verifySpace+0xa>
|
|
|
|
|
|
+ 1fe12: 88 e0 ldi r24, 0x08 ; 8
|
|
|
|
+ 1fe14: f5 df rcall .-22 ; 0x1fe00 <watchdogConfig>
|
|
|
|
+ 1fe16: ff cf rjmp .-2 ; 0x1fe16 <verifySpace+0xa>
|
|
while (1) // and busy-loop so that WD causes
|
|
while (1) // and busy-loop so that WD causes
|
|
; // a reset and app start.
|
|
; // a reset and app start.
|
|
}
|
|
}
|
|
putch(STK_INSYNC);
|
|
putch(STK_INSYNC);
|
|
- 1fe10: 84 e1 ldi r24, 0x14 ; 20
|
|
|
|
|
|
+ 1fe18: 84 e1 ldi r24, 0x14 ; 20
|
|
}
|
|
}
|
|
- 1fe12: de cf rjmp .-68 ; 0x1fdd0 <putch>
|
|
|
|
|
|
+ 1fe1a: de cf rjmp .-68 ; 0x1fdd8 <putch>
|
|
|
|
|
|
-0001fe14 <getNch>:
|
|
|
|
|
|
+0001fe1c <getNch>:
|
|
::[count] "M" (UART_B_VALUE)
|
|
::[count] "M" (UART_B_VALUE)
|
|
);
|
|
);
|
|
}
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
|
|
void getNch(uint8_t count) {
|
|
void getNch(uint8_t count) {
|
|
- 1fe14: 1f 93 push r17
|
|
|
|
- 1fe16: 18 2f mov r17, r24
|
|
|
|
|
|
+ 1fe1c: 1f 93 push r17
|
|
|
|
+ 1fe1e: 18 2f mov r17, r24
|
|
do getch(); while (--count);
|
|
do getch(); while (--count);
|
|
- 1fe18: e3 df rcall .-58 ; 0x1fde0 <getch>
|
|
|
|
- 1fe1a: 11 50 subi r17, 0x01 ; 1
|
|
|
|
- 1fe1c: e9 f7 brne .-6 ; 0x1fe18 <getNch+0x4>
|
|
|
|
|
|
+ 1fe20: e3 df rcall .-58 ; 0x1fde8 <getch>
|
|
|
|
+ 1fe22: 11 50 subi r17, 0x01 ; 1
|
|
|
|
+ 1fe24: e9 f7 brne .-6 ; 0x1fe20 <getNch+0x4>
|
|
verifySpace();
|
|
verifySpace();
|
|
- 1fe1e: f2 df rcall .-28 ; 0x1fe04 <verifySpace>
|
|
|
|
|
|
+ 1fe26: f2 df rcall .-28 ; 0x1fe0c <verifySpace>
|
|
}
|
|
}
|
|
- 1fe20: 1f 91 pop r17
|
|
|
|
- 1fe22: 08 95 ret
|
|
|
|
|
|
+ 1fe28: 1f 91 pop r17
|
|
|
|
+ 1fe2a: 08 95 ret
|
|
|
|
|
|
-0001fe24 <appStart>:
|
|
|
|
|
|
+0001fe2c <appStart>:
|
|
|
|
|
|
void appStart(uint8_t rstFlags) {
|
|
void appStart(uint8_t rstFlags) {
|
|
// save the reset flags in the designated register
|
|
// save the reset flags in the designated register
|
|
// This can be saved in a main program by putting code in .init0 (which
|
|
// This can be saved in a main program by putting code in .init0 (which
|
|
// executes before normal c init code) to save R2 to a global variable.
|
|
// executes before normal c init code) to save R2 to a global variable.
|
|
__asm__ __volatile__ ("mov r2, %0\n" :: "r" (rstFlags));
|
|
__asm__ __volatile__ ("mov r2, %0\n" :: "r" (rstFlags));
|
|
- 1fe24: 28 2e mov r2, r24
|
|
|
|
|
|
+ 1fe2c: 28 2e mov r2, r24
|
|
|
|
|
|
watchdogConfig(WATCHDOG_OFF);
|
|
watchdogConfig(WATCHDOG_OFF);
|
|
- 1fe26: 80 e0 ldi r24, 0x00 ; 0
|
|
|
|
- 1fe28: e7 df rcall .-50 ; 0x1fdf8 <watchdogConfig>
|
|
|
|
|
|
+ 1fe2e: 80 e0 ldi r24, 0x00 ; 0
|
|
|
|
+ 1fe30: e7 df rcall .-50 ; 0x1fe00 <watchdogConfig>
|
|
__asm__ __volatile__ (
|
|
__asm__ __volatile__ (
|
|
- 1fe2a: ee 27 eor r30, r30
|
|
|
|
- 1fe2c: ff 27 eor r31, r31
|
|
|
|
- 1fe2e: 09 94 ijmp
|
|
|
|
-
|
|
|
|
-0001fe30 <__eerd_byte_m1280>:
|
|
|
|
- 1fe30: f9 99 sbic 0x1f, 1 ; 31
|
|
|
|
- 1fe32: fe cf rjmp .-4 ; 0x1fe30 <__eerd_byte_m1280>
|
|
|
|
- 1fe34: 92 bd out 0x22, r25 ; 34
|
|
|
|
- 1fe36: 81 bd out 0x21, r24 ; 33
|
|
|
|
- 1fe38: f8 9a sbi 0x1f, 0 ; 31
|
|
|
|
- 1fe3a: 99 27 eor r25, r25
|
|
|
|
- 1fe3c: 80 b5 in r24, 0x20 ; 32
|
|
|
|
- 1fe3e: 08 95 ret
|
|
|
|
-
|
|
|
|
-0001fe40 <__eewr_byte_m1280>:
|
|
|
|
- 1fe40: 26 2f mov r18, r22
|
|
|
|
-
|
|
|
|
-0001fe42 <__eewr_r18_m1280>:
|
|
|
|
- 1fe42: f9 99 sbic 0x1f, 1 ; 31
|
|
|
|
- 1fe44: fe cf rjmp .-4 ; 0x1fe42 <__eewr_r18_m1280>
|
|
|
|
- 1fe46: 1f ba out 0x1f, r1 ; 31
|
|
|
|
- 1fe48: 92 bd out 0x22, r25 ; 34
|
|
|
|
- 1fe4a: 81 bd out 0x21, r24 ; 33
|
|
|
|
- 1fe4c: 20 bd out 0x20, r18 ; 32
|
|
|
|
- 1fe4e: 0f b6 in r0, 0x3f ; 63
|
|
|
|
- 1fe50: f8 94 cli
|
|
|
|
- 1fe52: fa 9a sbi 0x1f, 2 ; 31
|
|
|
|
- 1fe54: f9 9a sbi 0x1f, 1 ; 31
|
|
|
|
- 1fe56: 0f be out 0x3f, r0 ; 63
|
|
|
|
- 1fe58: 01 96 adiw r24, 0x01 ; 1
|
|
|
|
- 1fe5a: 08 95 ret
|
|
|
|
|
|
+ 1fe32: ee 27 eor r30, r30
|
|
|
|
+ 1fe34: ff 27 eor r31, r31
|
|
|
|
+ 1fe36: 09 94 ijmp
|
|
|
|
+
|
|
|
|
+0001fe38 <__eerd_byte_m1280>:
|
|
|
|
+ 1fe38: f9 99 sbic 0x1f, 1 ; 31
|
|
|
|
+ 1fe3a: fe cf rjmp .-4 ; 0x1fe38 <__eerd_byte_m1280>
|
|
|
|
+ 1fe3c: 92 bd out 0x22, r25 ; 34
|
|
|
|
+ 1fe3e: 81 bd out 0x21, r24 ; 33
|
|
|
|
+ 1fe40: f8 9a sbi 0x1f, 0 ; 31
|
|
|
|
+ 1fe42: 99 27 eor r25, r25
|
|
|
|
+ 1fe44: 80 b5 in r24, 0x20 ; 32
|
|
|
|
+ 1fe46: 08 95 ret
|
|
|
|
+
|
|
|
|
+0001fe48 <__eewr_byte_m1280>:
|
|
|
|
+ 1fe48: 26 2f mov r18, r22
|
|
|
|
+
|
|
|
|
+0001fe4a <__eewr_r18_m1280>:
|
|
|
|
+ 1fe4a: f9 99 sbic 0x1f, 1 ; 31
|
|
|
|
+ 1fe4c: fe cf rjmp .-4 ; 0x1fe4a <__eewr_r18_m1280>
|
|
|
|
+ 1fe4e: 1f ba out 0x1f, r1 ; 31
|
|
|
|
+ 1fe50: 92 bd out 0x22, r25 ; 34
|
|
|
|
+ 1fe52: 81 bd out 0x21, r24 ; 33
|
|
|
|
+ 1fe54: 20 bd out 0x20, r18 ; 32
|
|
|
|
+ 1fe56: 0f b6 in r0, 0x3f ; 63
|
|
|
|
+ 1fe58: f8 94 cli
|
|
|
|
+ 1fe5a: fa 9a sbi 0x1f, 2 ; 31
|
|
|
|
+ 1fe5c: f9 9a sbi 0x1f, 1 ; 31
|
|
|
|
+ 1fe5e: 0f be out 0x3f, r0 ; 63
|
|
|
|
+ 1fe60: 01 96 adiw r24, 0x01 ; 1
|
|
|
|
+ 1fe62: 08 95 ret
|