hfi1_user.h 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427
  1. /*
  2. *
  3. * This file is provided under a dual BSD/GPLv2 license. When using or
  4. * redistributing this file, you may do so under either license.
  5. *
  6. * GPL LICENSE SUMMARY
  7. *
  8. * Copyright(c) 2015 Intel Corporation.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of version 2 of the GNU General Public License as
  12. * published by the Free Software Foundation.
  13. *
  14. * This program is distributed in the hope that it will be useful, but
  15. * WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  17. * General Public License for more details.
  18. *
  19. * BSD LICENSE
  20. *
  21. * Copyright(c) 2015 Intel Corporation.
  22. *
  23. * Redistribution and use in source and binary forms, with or without
  24. * modification, are permitted provided that the following conditions
  25. * are met:
  26. *
  27. * - Redistributions of source code must retain the above copyright
  28. * notice, this list of conditions and the following disclaimer.
  29. * - Redistributions in binary form must reproduce the above copyright
  30. * notice, this list of conditions and the following disclaimer in
  31. * the documentation and/or other materials provided with the
  32. * distribution.
  33. * - Neither the name of Intel Corporation nor the names of its
  34. * contributors may be used to endorse or promote products derived
  35. * from this software without specific prior written permission.
  36. *
  37. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  38. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  39. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  40. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  41. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  42. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  43. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  44. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  45. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  46. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  47. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  48. *
  49. */
  50. /*
  51. * This file contains defines, structures, etc. that are used
  52. * to communicate between kernel and user code.
  53. */
  54. #ifndef _LINUX__HFI1_USER_H
  55. #define _LINUX__HFI1_USER_H
  56. #include <linux/types.h>
  57. /*
  58. * This version number is given to the driver by the user code during
  59. * initialization in the spu_userversion field of hfi1_user_info, so
  60. * the driver can check for compatibility with user code.
  61. *
  62. * The major version changes when data structures change in an incompatible
  63. * way. The driver must be the same for initialization to succeed.
  64. */
  65. #define HFI1_USER_SWMAJOR 4
  66. /*
  67. * Minor version differences are always compatible
  68. * a within a major version, however if user software is larger
  69. * than driver software, some new features and/or structure fields
  70. * may not be implemented; the user code must deal with this if it
  71. * cares, or it must abort after initialization reports the difference.
  72. */
  73. #define HFI1_USER_SWMINOR 0
  74. /*
  75. * Set of HW and driver capability/feature bits.
  76. * These bit values are used to configure enabled/disabled HW and
  77. * driver features. The same set of bits are communicated to user
  78. * space.
  79. */
  80. #define HFI1_CAP_DMA_RTAIL (1UL << 0) /* Use DMA'ed RTail value */
  81. #define HFI1_CAP_SDMA (1UL << 1) /* Enable SDMA support */
  82. #define HFI1_CAP_SDMA_AHG (1UL << 2) /* Enable SDMA AHG support */
  83. #define HFI1_CAP_EXTENDED_PSN (1UL << 3) /* Enable Extended PSN support */
  84. #define HFI1_CAP_HDRSUPP (1UL << 4) /* Enable Header Suppression */
  85. /* 1UL << 5 unused */
  86. #define HFI1_CAP_USE_SDMA_HEAD (1UL << 6) /* DMA Hdr Q tail vs. use CSR */
  87. #define HFI1_CAP_MULTI_PKT_EGR (1UL << 7) /* Enable multi-packet Egr buffs*/
  88. #define HFI1_CAP_NODROP_RHQ_FULL (1UL << 8) /* Don't drop on Hdr Q full */
  89. #define HFI1_CAP_NODROP_EGR_FULL (1UL << 9) /* Don't drop on EGR buffs full */
  90. #define HFI1_CAP_TID_UNMAP (1UL << 10) /* Enable Expected TID caching */
  91. #define HFI1_CAP_PRINT_UNIMPL (1UL << 11) /* Show for unimplemented feats */
  92. #define HFI1_CAP_ALLOW_PERM_JKEY (1UL << 12) /* Allow use of permissive JKEY */
  93. #define HFI1_CAP_NO_INTEGRITY (1UL << 13) /* Enable ctxt integrity checks */
  94. #define HFI1_CAP_PKEY_CHECK (1UL << 14) /* Enable ctxt PKey checking */
  95. #define HFI1_CAP_STATIC_RATE_CTRL (1UL << 15) /* Allow PBC.StaticRateControl */
  96. /* 1UL << 16 unused */
  97. #define HFI1_CAP_SDMA_HEAD_CHECK (1UL << 17) /* SDMA head checking */
  98. #define HFI1_CAP_EARLY_CREDIT_RETURN (1UL << 18) /* early credit return */
  99. #define HFI1_RCVHDR_ENTSIZE_2 (1UL << 0)
  100. #define HFI1_RCVHDR_ENTSIZE_16 (1UL << 1)
  101. #define HFI1_RCVDHR_ENTSIZE_32 (1UL << 2)
  102. /*
  103. * If the unit is specified via open, HFI choice is fixed. If port is
  104. * specified, it's also fixed. Otherwise we try to spread contexts
  105. * across ports and HFIs, using different algorithms. WITHIN is
  106. * the old default, prior to this mechanism.
  107. */
  108. #define HFI1_ALG_ACROSS 0 /* round robin contexts across HFIs, then
  109. * ports; this is the default */
  110. #define HFI1_ALG_WITHIN 1 /* use all contexts on an HFI (round robin
  111. * active ports within), then next HFI */
  112. #define HFI1_ALG_COUNT 2 /* number of algorithm choices */
  113. /* User commands. */
  114. #define HFI1_CMD_ASSIGN_CTXT 1 /* allocate HFI and context */
  115. #define HFI1_CMD_CTXT_INFO 2 /* find out what resources we got */
  116. #define HFI1_CMD_USER_INFO 3 /* set up userspace */
  117. #define HFI1_CMD_TID_UPDATE 4 /* update expected TID entries */
  118. #define HFI1_CMD_TID_FREE 5 /* free expected TID entries */
  119. #define HFI1_CMD_CREDIT_UPD 6 /* force an update of PIO credit */
  120. #define HFI1_CMD_SDMA_STATUS_UPD 7 /* force update of SDMA status ring */
  121. #define HFI1_CMD_RECV_CTRL 8 /* control receipt of packets */
  122. #define HFI1_CMD_POLL_TYPE 9 /* set the kind of polling we want */
  123. #define HFI1_CMD_ACK_EVENT 10 /* ack & clear user status bits */
  124. #define HFI1_CMD_SET_PKEY 11 /* set context's pkey */
  125. #define HFI1_CMD_CTXT_RESET 12 /* reset context's HW send context */
  126. /* separate EPROM commands from normal PSM commands */
  127. #define HFI1_CMD_EP_INFO 64 /* read EPROM device ID */
  128. #define HFI1_CMD_EP_ERASE_CHIP 65 /* erase whole EPROM */
  129. #define HFI1_CMD_EP_ERASE_P0 66 /* erase EPROM partition 0 */
  130. #define HFI1_CMD_EP_ERASE_P1 67 /* erase EPROM partition 1 */
  131. #define HFI1_CMD_EP_READ_P0 68 /* read EPROM partition 0 */
  132. #define HFI1_CMD_EP_READ_P1 69 /* read EPROM partition 1 */
  133. #define HFI1_CMD_EP_WRITE_P0 70 /* write EPROM partition 0 */
  134. #define HFI1_CMD_EP_WRITE_P1 71 /* write EPROM partition 1 */
  135. #define _HFI1_EVENT_FROZEN_BIT 0
  136. #define _HFI1_EVENT_LINKDOWN_BIT 1
  137. #define _HFI1_EVENT_LID_CHANGE_BIT 2
  138. #define _HFI1_EVENT_LMC_CHANGE_BIT 3
  139. #define _HFI1_EVENT_SL2VL_CHANGE_BIT 4
  140. #define _HFI1_MAX_EVENT_BIT _HFI1_EVENT_SL2VL_CHANGE_BIT
  141. #define HFI1_EVENT_FROZEN (1UL << _HFI1_EVENT_FROZEN_BIT)
  142. #define HFI1_EVENT_LINKDOWN_BIT (1UL << _HFI1_EVENT_LINKDOWN_BIT)
  143. #define HFI1_EVENT_LID_CHANGE_BIT (1UL << _HFI1_EVENT_LID_CHANGE_BIT)
  144. #define HFI1_EVENT_LMC_CHANGE_BIT (1UL << _HFI1_EVENT_LMC_CHANGE_BIT)
  145. #define HFI1_EVENT_SL2VL_CHANGE_BIT (1UL << _HFI1_EVENT_SL2VL_CHANGE_BIT)
  146. /*
  147. * These are the status bits readable (in ASCII form, 64bit value)
  148. * from the "status" sysfs file. For binary compatibility, values
  149. * must remain as is; removed states can be reused for different
  150. * purposes.
  151. */
  152. #define HFI1_STATUS_INITTED 0x1 /* basic initialization done */
  153. /* Chip has been found and initialized */
  154. #define HFI1_STATUS_CHIP_PRESENT 0x20
  155. /* IB link is at ACTIVE, usable for data traffic */
  156. #define HFI1_STATUS_IB_READY 0x40
  157. /* link is configured, LID, MTU, etc. have been set */
  158. #define HFI1_STATUS_IB_CONF 0x80
  159. /* A Fatal hardware error has occurred. */
  160. #define HFI1_STATUS_HWERROR 0x200
  161. /*
  162. * Number of supported shared contexts.
  163. * This is the maximum number of software contexts that can share
  164. * a hardware send/receive context.
  165. */
  166. #define HFI1_MAX_SHARED_CTXTS 8
  167. /*
  168. * Poll types
  169. */
  170. #define HFI1_POLL_TYPE_ANYRCV 0x0
  171. #define HFI1_POLL_TYPE_URGENT 0x1
  172. /*
  173. * This structure is passed to the driver to tell it where
  174. * user code buffers are, sizes, etc. The offsets and sizes of the
  175. * fields must remain unchanged, for binary compatibility. It can
  176. * be extended, if userversion is changed so user code can tell, if needed
  177. */
  178. struct hfi1_user_info {
  179. /*
  180. * version of user software, to detect compatibility issues.
  181. * Should be set to HFI1_USER_SWVERSION.
  182. */
  183. __u32 userversion;
  184. __u16 pad;
  185. /* HFI selection algorithm, if unit has not selected */
  186. __u16 hfi1_alg;
  187. /*
  188. * If two or more processes wish to share a context, each process
  189. * must set the subcontext_cnt and subcontext_id to the same
  190. * values. The only restriction on the subcontext_id is that
  191. * it be unique for a given node.
  192. */
  193. __u16 subctxt_cnt;
  194. __u16 subctxt_id;
  195. /* 128bit UUID passed in by PSM. */
  196. __u8 uuid[16];
  197. };
  198. struct hfi1_ctxt_info {
  199. __u64 runtime_flags; /* chip/drv runtime flags (HFI1_CAP_*) */
  200. __u32 rcvegr_size; /* size of each eager buffer */
  201. __u16 num_active; /* number of active units */
  202. __u16 unit; /* unit (chip) assigned to caller */
  203. __u16 ctxt; /* ctxt on unit assigned to caller */
  204. __u16 subctxt; /* subctxt on unit assigned to caller */
  205. __u16 rcvtids; /* number of Rcv TIDs for this context */
  206. __u16 credits; /* number of PIO credits for this context */
  207. __u16 numa_node; /* NUMA node of the assigned device */
  208. __u16 rec_cpu; /* cpu # for affinity (0xffff if none) */
  209. __u16 send_ctxt; /* send context in use by this user context */
  210. __u16 egrtids; /* number of RcvArray entries for Eager Rcvs */
  211. __u16 rcvhdrq_cnt; /* number of RcvHdrQ entries */
  212. __u16 rcvhdrq_entsize; /* size (in bytes) for each RcvHdrQ entry */
  213. __u16 sdma_ring_size; /* number of entries in SDMA request ring */
  214. };
  215. struct hfi1_tid_info {
  216. /* virtual address of first page in transfer */
  217. __u64 vaddr;
  218. /* pointer to tid array. this array is big enough */
  219. __u64 tidlist;
  220. /* number of tids programmed by this request */
  221. __u32 tidcnt;
  222. /* length of transfer buffer programmed by this request */
  223. __u32 length;
  224. /*
  225. * pointer to bitmap of TIDs used for this call;
  226. * checked for being large enough at open
  227. */
  228. __u64 tidmap;
  229. };
  230. struct hfi1_cmd {
  231. __u32 type; /* command type */
  232. __u32 len; /* length of struct pointed to by add */
  233. __u64 addr; /* pointer to user structure */
  234. };
  235. enum hfi1_sdma_comp_state {
  236. FREE = 0,
  237. QUEUED,
  238. COMPLETE,
  239. ERROR
  240. };
  241. /*
  242. * SDMA completion ring entry
  243. */
  244. struct hfi1_sdma_comp_entry {
  245. __u32 status;
  246. __u32 errcode;
  247. };
  248. /*
  249. * Device status and notifications from driver to user-space.
  250. */
  251. struct hfi1_status {
  252. __u64 dev; /* device/hw status bits */
  253. __u64 port; /* port state and status bits */
  254. char freezemsg[0];
  255. };
  256. /*
  257. * This structure is returned by the driver immediately after
  258. * open to get implementation-specific info, and info specific to this
  259. * instance.
  260. *
  261. * This struct must have explicit pad fields where type sizes
  262. * may result in different alignments between 32 and 64 bit
  263. * programs, since the 64 bit * bit kernel requires the user code
  264. * to have matching offsets
  265. */
  266. struct hfi1_base_info {
  267. /* version of hardware, for feature checking. */
  268. __u32 hw_version;
  269. /* version of software, for feature checking. */
  270. __u32 sw_version;
  271. /* Job key */
  272. __u16 jkey;
  273. __u16 padding1;
  274. /*
  275. * The special QP (queue pair) value that identifies PSM
  276. * protocol packet from standard IB packets.
  277. */
  278. __u32 bthqp;
  279. /* PIO credit return address, */
  280. __u64 sc_credits_addr;
  281. /*
  282. * Base address of write-only pio buffers for this process.
  283. * Each buffer has sendpio_credits*64 bytes.
  284. */
  285. __u64 pio_bufbase_sop;
  286. /*
  287. * Base address of write-only pio buffers for this process.
  288. * Each buffer has sendpio_credits*64 bytes.
  289. */
  290. __u64 pio_bufbase;
  291. /* address where receive buffer queue is mapped into */
  292. __u64 rcvhdr_bufbase;
  293. /* base address of Eager receive buffers. */
  294. __u64 rcvegr_bufbase;
  295. /* base address of SDMA completion ring */
  296. __u64 sdma_comp_bufbase;
  297. /*
  298. * User register base for init code, not to be used directly by
  299. * protocol or applications. Always maps real chip register space.
  300. * the register addresses are:
  301. * ur_rcvhdrhead, ur_rcvhdrtail, ur_rcvegrhead, ur_rcvegrtail,
  302. * ur_rcvtidflow
  303. */
  304. __u64 user_regbase;
  305. /* notification events */
  306. __u64 events_bufbase;
  307. /* status page */
  308. __u64 status_bufbase;
  309. /* rcvhdrtail update */
  310. __u64 rcvhdrtail_base;
  311. /*
  312. * shared memory pages for subctxts if ctxt is shared; these cover
  313. * all the processes in the group sharing a single context.
  314. * all have enough space for the num_subcontexts value on this job.
  315. */
  316. __u64 subctxt_uregbase;
  317. __u64 subctxt_rcvegrbuf;
  318. __u64 subctxt_rcvhdrbuf;
  319. };
  320. enum sdma_req_opcode {
  321. EXPECTED = 0,
  322. EAGER
  323. };
  324. #define HFI1_SDMA_REQ_VERSION_MASK 0xF
  325. #define HFI1_SDMA_REQ_VERSION_SHIFT 0x0
  326. #define HFI1_SDMA_REQ_OPCODE_MASK 0xF
  327. #define HFI1_SDMA_REQ_OPCODE_SHIFT 0x4
  328. #define HFI1_SDMA_REQ_IOVCNT_MASK 0xFF
  329. #define HFI1_SDMA_REQ_IOVCNT_SHIFT 0x8
  330. struct sdma_req_info {
  331. /*
  332. * bits 0-3 - version (currently unused)
  333. * bits 4-7 - opcode (enum sdma_req_opcode)
  334. * bits 8-15 - io vector count
  335. */
  336. __u16 ctrl;
  337. /*
  338. * Number of fragments contained in this request.
  339. * User-space has already computed how many
  340. * fragment-sized packet the user buffer will be
  341. * split into.
  342. */
  343. __u16 npkts;
  344. /*
  345. * Size of each fragment the user buffer will be
  346. * split into.
  347. */
  348. __u16 fragsize;
  349. /*
  350. * Index of the slot in the SDMA completion ring
  351. * this request should be using. User-space is
  352. * in charge of managing its own ring.
  353. */
  354. __u16 comp_idx;
  355. } __attribute__((packed));
  356. /*
  357. * SW KDETH header.
  358. * swdata is SW defined portion.
  359. */
  360. struct hfi1_kdeth_header {
  361. __le32 ver_tid_offset;
  362. __le16 jkey;
  363. __le16 hcrc;
  364. __le32 swdata[7];
  365. } __attribute__((packed));
  366. /*
  367. * Structure describing the headers that User space uses. The
  368. * structure above is a subset of this one.
  369. */
  370. struct hfi1_pkt_header {
  371. __le16 pbc[4];
  372. __be16 lrh[4];
  373. __be32 bth[3];
  374. struct hfi1_kdeth_header kdeth;
  375. } __attribute__((packed));
  376. /*
  377. * The list of usermode accessible registers.
  378. */
  379. enum hfi1_ureg {
  380. /* (RO) DMA RcvHdr to be used next. */
  381. ur_rcvhdrtail = 0,
  382. /* (RW) RcvHdr entry to be processed next by host. */
  383. ur_rcvhdrhead = 1,
  384. /* (RO) Index of next Eager index to use. */
  385. ur_rcvegrindextail = 2,
  386. /* (RW) Eager TID to be processed next */
  387. ur_rcvegrindexhead = 3,
  388. /* (RO) Receive Eager Offset Tail */
  389. ur_rcvegroffsettail = 4,
  390. /* For internal use only; max register number. */
  391. ur_maxreg,
  392. /* (RW) Receive TID flow table */
  393. ur_rcvtidflowtable = 256
  394. };
  395. #endif /* _LINIUX__HFI1_USER_H */