i915_drm.h 35 KB

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  1. /*
  2. * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the
  14. * next paragraph) shall be included in all copies or substantial portions
  15. * of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18. * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  20. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  21. * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  22. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  23. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24. *
  25. */
  26. #ifndef _I915_DRM_H_
  27. #define _I915_DRM_H_
  28. #include <drm/drm.h>
  29. /* Please note that modifications to all structs defined here are
  30. * subject to backwards-compatibility constraints.
  31. */
  32. /**
  33. * DOC: uevents generated by i915 on it's device node
  34. *
  35. * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
  36. * event from the gpu l3 cache. Additional information supplied is ROW,
  37. * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep
  38. * track of these events and if a specific cache-line seems to have a
  39. * persistent error remap it with the l3 remapping tool supplied in
  40. * intel-gpu-tools. The value supplied with the event is always 1.
  41. *
  42. * I915_ERROR_UEVENT - Generated upon error detection, currently only via
  43. * hangcheck. The error detection event is a good indicator of when things
  44. * began to go badly. The value supplied with the event is a 1 upon error
  45. * detection, and a 0 upon reset completion, signifying no more error
  46. * exists. NOTE: Disabling hangcheck or reset via module parameter will
  47. * cause the related events to not be seen.
  48. *
  49. * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
  50. * the GPU. The value supplied with the event is always 1. NOTE: Disable
  51. * reset via module parameter will cause this event to not be seen.
  52. */
  53. #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR"
  54. #define I915_ERROR_UEVENT "ERROR"
  55. #define I915_RESET_UEVENT "RESET"
  56. /* Each region is a minimum of 16k, and there are at most 255 of them.
  57. */
  58. #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
  59. * of chars for next/prev indices */
  60. #define I915_LOG_MIN_TEX_REGION_SIZE 14
  61. typedef struct _drm_i915_init {
  62. enum {
  63. I915_INIT_DMA = 0x01,
  64. I915_CLEANUP_DMA = 0x02,
  65. I915_RESUME_DMA = 0x03
  66. } func;
  67. unsigned int mmio_offset;
  68. int sarea_priv_offset;
  69. unsigned int ring_start;
  70. unsigned int ring_end;
  71. unsigned int ring_size;
  72. unsigned int front_offset;
  73. unsigned int back_offset;
  74. unsigned int depth_offset;
  75. unsigned int w;
  76. unsigned int h;
  77. unsigned int pitch;
  78. unsigned int pitch_bits;
  79. unsigned int back_pitch;
  80. unsigned int depth_pitch;
  81. unsigned int cpp;
  82. unsigned int chipset;
  83. } drm_i915_init_t;
  84. typedef struct _drm_i915_sarea {
  85. struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
  86. int last_upload; /* last time texture was uploaded */
  87. int last_enqueue; /* last time a buffer was enqueued */
  88. int last_dispatch; /* age of the most recently dispatched buffer */
  89. int ctxOwner; /* last context to upload state */
  90. int texAge;
  91. int pf_enabled; /* is pageflipping allowed? */
  92. int pf_active;
  93. int pf_current_page; /* which buffer is being displayed? */
  94. int perf_boxes; /* performance boxes to be displayed */
  95. int width, height; /* screen size in pixels */
  96. drm_handle_t front_handle;
  97. int front_offset;
  98. int front_size;
  99. drm_handle_t back_handle;
  100. int back_offset;
  101. int back_size;
  102. drm_handle_t depth_handle;
  103. int depth_offset;
  104. int depth_size;
  105. drm_handle_t tex_handle;
  106. int tex_offset;
  107. int tex_size;
  108. int log_tex_granularity;
  109. int pitch;
  110. int rotation; /* 0, 90, 180 or 270 */
  111. int rotated_offset;
  112. int rotated_size;
  113. int rotated_pitch;
  114. int virtualX, virtualY;
  115. unsigned int front_tiled;
  116. unsigned int back_tiled;
  117. unsigned int depth_tiled;
  118. unsigned int rotated_tiled;
  119. unsigned int rotated2_tiled;
  120. int pipeA_x;
  121. int pipeA_y;
  122. int pipeA_w;
  123. int pipeA_h;
  124. int pipeB_x;
  125. int pipeB_y;
  126. int pipeB_w;
  127. int pipeB_h;
  128. /* fill out some space for old userspace triple buffer */
  129. drm_handle_t unused_handle;
  130. __u32 unused1, unused2, unused3;
  131. /* buffer object handles for static buffers. May change
  132. * over the lifetime of the client.
  133. */
  134. __u32 front_bo_handle;
  135. __u32 back_bo_handle;
  136. __u32 unused_bo_handle;
  137. __u32 depth_bo_handle;
  138. } drm_i915_sarea_t;
  139. /* due to userspace building against these headers we need some compat here */
  140. #define planeA_x pipeA_x
  141. #define planeA_y pipeA_y
  142. #define planeA_w pipeA_w
  143. #define planeA_h pipeA_h
  144. #define planeB_x pipeB_x
  145. #define planeB_y pipeB_y
  146. #define planeB_w pipeB_w
  147. #define planeB_h pipeB_h
  148. /* Flags for perf_boxes
  149. */
  150. #define I915_BOX_RING_EMPTY 0x1
  151. #define I915_BOX_FLIP 0x2
  152. #define I915_BOX_WAIT 0x4
  153. #define I915_BOX_TEXTURE_LOAD 0x8
  154. #define I915_BOX_LOST_CONTEXT 0x10
  155. /*
  156. * i915 specific ioctls.
  157. *
  158. * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie
  159. * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset
  160. * against DRM_COMMAND_BASE and should be between [0x0, 0x60).
  161. */
  162. #define DRM_I915_INIT 0x00
  163. #define DRM_I915_FLUSH 0x01
  164. #define DRM_I915_FLIP 0x02
  165. #define DRM_I915_BATCHBUFFER 0x03
  166. #define DRM_I915_IRQ_EMIT 0x04
  167. #define DRM_I915_IRQ_WAIT 0x05
  168. #define DRM_I915_GETPARAM 0x06
  169. #define DRM_I915_SETPARAM 0x07
  170. #define DRM_I915_ALLOC 0x08
  171. #define DRM_I915_FREE 0x09
  172. #define DRM_I915_INIT_HEAP 0x0a
  173. #define DRM_I915_CMDBUFFER 0x0b
  174. #define DRM_I915_DESTROY_HEAP 0x0c
  175. #define DRM_I915_SET_VBLANK_PIPE 0x0d
  176. #define DRM_I915_GET_VBLANK_PIPE 0x0e
  177. #define DRM_I915_VBLANK_SWAP 0x0f
  178. #define DRM_I915_HWS_ADDR 0x11
  179. #define DRM_I915_GEM_INIT 0x13
  180. #define DRM_I915_GEM_EXECBUFFER 0x14
  181. #define DRM_I915_GEM_PIN 0x15
  182. #define DRM_I915_GEM_UNPIN 0x16
  183. #define DRM_I915_GEM_BUSY 0x17
  184. #define DRM_I915_GEM_THROTTLE 0x18
  185. #define DRM_I915_GEM_ENTERVT 0x19
  186. #define DRM_I915_GEM_LEAVEVT 0x1a
  187. #define DRM_I915_GEM_CREATE 0x1b
  188. #define DRM_I915_GEM_PREAD 0x1c
  189. #define DRM_I915_GEM_PWRITE 0x1d
  190. #define DRM_I915_GEM_MMAP 0x1e
  191. #define DRM_I915_GEM_SET_DOMAIN 0x1f
  192. #define DRM_I915_GEM_SW_FINISH 0x20
  193. #define DRM_I915_GEM_SET_TILING 0x21
  194. #define DRM_I915_GEM_GET_TILING 0x22
  195. #define DRM_I915_GEM_GET_APERTURE 0x23
  196. #define DRM_I915_GEM_MMAP_GTT 0x24
  197. #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
  198. #define DRM_I915_GEM_MADVISE 0x26
  199. #define DRM_I915_OVERLAY_PUT_IMAGE 0x27
  200. #define DRM_I915_OVERLAY_ATTRS 0x28
  201. #define DRM_I915_GEM_EXECBUFFER2 0x29
  202. #define DRM_I915_GET_SPRITE_COLORKEY 0x2a
  203. #define DRM_I915_SET_SPRITE_COLORKEY 0x2b
  204. #define DRM_I915_GEM_WAIT 0x2c
  205. #define DRM_I915_GEM_CONTEXT_CREATE 0x2d
  206. #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
  207. #define DRM_I915_GEM_SET_CACHING 0x2f
  208. #define DRM_I915_GEM_GET_CACHING 0x30
  209. #define DRM_I915_REG_READ 0x31
  210. #define DRM_I915_GET_RESET_STATS 0x32
  211. #define DRM_I915_GEM_USERPTR 0x33
  212. #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34
  213. #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35
  214. #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
  215. #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
  216. #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
  217. #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
  218. #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
  219. #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
  220. #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
  221. #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
  222. #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
  223. #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
  224. #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
  225. #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
  226. #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
  227. #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
  228. #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
  229. #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
  230. #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
  231. #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
  232. #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
  233. #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
  234. #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
  235. #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
  236. #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
  237. #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
  238. #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
  239. #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
  240. #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
  241. #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
  242. #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
  243. #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
  244. #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
  245. #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
  246. #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
  247. #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
  248. #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
  249. #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
  250. #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
  251. #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
  252. #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
  253. #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
  254. #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
  255. #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
  256. #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
  257. #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
  258. #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
  259. #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
  260. #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
  261. #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
  262. #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
  263. #define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
  264. #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
  265. #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
  266. /* Allow drivers to submit batchbuffers directly to hardware, relying
  267. * on the security mechanisms provided by hardware.
  268. */
  269. typedef struct drm_i915_batchbuffer {
  270. int start; /* agp offset */
  271. int used; /* nr bytes in use */
  272. int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
  273. int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
  274. int num_cliprects; /* mulitpass with multiple cliprects? */
  275. struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */
  276. } drm_i915_batchbuffer_t;
  277. /* As above, but pass a pointer to userspace buffer which can be
  278. * validated by the kernel prior to sending to hardware.
  279. */
  280. typedef struct _drm_i915_cmdbuffer {
  281. char *buf; /* pointer to userspace command buffer */
  282. int sz; /* nr bytes in buf */
  283. int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
  284. int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
  285. int num_cliprects; /* mulitpass with multiple cliprects? */
  286. struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */
  287. } drm_i915_cmdbuffer_t;
  288. /* Userspace can request & wait on irq's:
  289. */
  290. typedef struct drm_i915_irq_emit {
  291. int *irq_seq;
  292. } drm_i915_irq_emit_t;
  293. typedef struct drm_i915_irq_wait {
  294. int irq_seq;
  295. } drm_i915_irq_wait_t;
  296. /* Ioctl to query kernel params:
  297. */
  298. #define I915_PARAM_IRQ_ACTIVE 1
  299. #define I915_PARAM_ALLOW_BATCHBUFFER 2
  300. #define I915_PARAM_LAST_DISPATCH 3
  301. #define I915_PARAM_CHIPSET_ID 4
  302. #define I915_PARAM_HAS_GEM 5
  303. #define I915_PARAM_NUM_FENCES_AVAIL 6
  304. #define I915_PARAM_HAS_OVERLAY 7
  305. #define I915_PARAM_HAS_PAGEFLIPPING 8
  306. #define I915_PARAM_HAS_EXECBUF2 9
  307. #define I915_PARAM_HAS_BSD 10
  308. #define I915_PARAM_HAS_BLT 11
  309. #define I915_PARAM_HAS_RELAXED_FENCING 12
  310. #define I915_PARAM_HAS_COHERENT_RINGS 13
  311. #define I915_PARAM_HAS_EXEC_CONSTANTS 14
  312. #define I915_PARAM_HAS_RELAXED_DELTA 15
  313. #define I915_PARAM_HAS_GEN7_SOL_RESET 16
  314. #define I915_PARAM_HAS_LLC 17
  315. #define I915_PARAM_HAS_ALIASING_PPGTT 18
  316. #define I915_PARAM_HAS_WAIT_TIMEOUT 19
  317. #define I915_PARAM_HAS_SEMAPHORES 20
  318. #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
  319. #define I915_PARAM_HAS_VEBOX 22
  320. #define I915_PARAM_HAS_SECURE_BATCHES 23
  321. #define I915_PARAM_HAS_PINNED_BATCHES 24
  322. #define I915_PARAM_HAS_EXEC_NO_RELOC 25
  323. #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
  324. #define I915_PARAM_HAS_WT 27
  325. #define I915_PARAM_CMD_PARSER_VERSION 28
  326. #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
  327. #define I915_PARAM_MMAP_VERSION 30
  328. #define I915_PARAM_HAS_BSD2 31
  329. #define I915_PARAM_REVISION 32
  330. #define I915_PARAM_SUBSLICE_TOTAL 33
  331. #define I915_PARAM_EU_TOTAL 34
  332. #define I915_PARAM_HAS_GPU_RESET 35
  333. #define I915_PARAM_HAS_RESOURCE_STREAMER 36
  334. typedef struct drm_i915_getparam {
  335. __s32 param;
  336. /*
  337. * WARNING: Using pointers instead of fixed-size u64 means we need to write
  338. * compat32 code. Don't repeat this mistake.
  339. */
  340. int *value;
  341. } drm_i915_getparam_t;
  342. /* Ioctl to set kernel params:
  343. */
  344. #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
  345. #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
  346. #define I915_SETPARAM_ALLOW_BATCHBUFFER 3
  347. #define I915_SETPARAM_NUM_USED_FENCES 4
  348. typedef struct drm_i915_setparam {
  349. int param;
  350. int value;
  351. } drm_i915_setparam_t;
  352. /* A memory manager for regions of shared memory:
  353. */
  354. #define I915_MEM_REGION_AGP 1
  355. typedef struct drm_i915_mem_alloc {
  356. int region;
  357. int alignment;
  358. int size;
  359. int *region_offset; /* offset from start of fb or agp */
  360. } drm_i915_mem_alloc_t;
  361. typedef struct drm_i915_mem_free {
  362. int region;
  363. int region_offset;
  364. } drm_i915_mem_free_t;
  365. typedef struct drm_i915_mem_init_heap {
  366. int region;
  367. int size;
  368. int start;
  369. } drm_i915_mem_init_heap_t;
  370. /* Allow memory manager to be torn down and re-initialized (eg on
  371. * rotate):
  372. */
  373. typedef struct drm_i915_mem_destroy_heap {
  374. int region;
  375. } drm_i915_mem_destroy_heap_t;
  376. /* Allow X server to configure which pipes to monitor for vblank signals
  377. */
  378. #define DRM_I915_VBLANK_PIPE_A 1
  379. #define DRM_I915_VBLANK_PIPE_B 2
  380. typedef struct drm_i915_vblank_pipe {
  381. int pipe;
  382. } drm_i915_vblank_pipe_t;
  383. /* Schedule buffer swap at given vertical blank:
  384. */
  385. typedef struct drm_i915_vblank_swap {
  386. drm_drawable_t drawable;
  387. enum drm_vblank_seq_type seqtype;
  388. unsigned int sequence;
  389. } drm_i915_vblank_swap_t;
  390. typedef struct drm_i915_hws_addr {
  391. __u64 addr;
  392. } drm_i915_hws_addr_t;
  393. struct drm_i915_gem_init {
  394. /**
  395. * Beginning offset in the GTT to be managed by the DRM memory
  396. * manager.
  397. */
  398. __u64 gtt_start;
  399. /**
  400. * Ending offset in the GTT to be managed by the DRM memory
  401. * manager.
  402. */
  403. __u64 gtt_end;
  404. };
  405. struct drm_i915_gem_create {
  406. /**
  407. * Requested size for the object.
  408. *
  409. * The (page-aligned) allocated size for the object will be returned.
  410. */
  411. __u64 size;
  412. /**
  413. * Returned handle for the object.
  414. *
  415. * Object handles are nonzero.
  416. */
  417. __u32 handle;
  418. __u32 pad;
  419. };
  420. struct drm_i915_gem_pread {
  421. /** Handle for the object being read. */
  422. __u32 handle;
  423. __u32 pad;
  424. /** Offset into the object to read from */
  425. __u64 offset;
  426. /** Length of data to read */
  427. __u64 size;
  428. /**
  429. * Pointer to write the data into.
  430. *
  431. * This is a fixed-size type for 32/64 compatibility.
  432. */
  433. __u64 data_ptr;
  434. };
  435. struct drm_i915_gem_pwrite {
  436. /** Handle for the object being written to. */
  437. __u32 handle;
  438. __u32 pad;
  439. /** Offset into the object to write to */
  440. __u64 offset;
  441. /** Length of data to write */
  442. __u64 size;
  443. /**
  444. * Pointer to read the data from.
  445. *
  446. * This is a fixed-size type for 32/64 compatibility.
  447. */
  448. __u64 data_ptr;
  449. };
  450. struct drm_i915_gem_mmap {
  451. /** Handle for the object being mapped. */
  452. __u32 handle;
  453. __u32 pad;
  454. /** Offset in the object to map. */
  455. __u64 offset;
  456. /**
  457. * Length of data to map.
  458. *
  459. * The value will be page-aligned.
  460. */
  461. __u64 size;
  462. /**
  463. * Returned pointer the data was mapped at.
  464. *
  465. * This is a fixed-size type for 32/64 compatibility.
  466. */
  467. __u64 addr_ptr;
  468. /**
  469. * Flags for extended behaviour.
  470. *
  471. * Added in version 2.
  472. */
  473. __u64 flags;
  474. #define I915_MMAP_WC 0x1
  475. };
  476. struct drm_i915_gem_mmap_gtt {
  477. /** Handle for the object being mapped. */
  478. __u32 handle;
  479. __u32 pad;
  480. /**
  481. * Fake offset to use for subsequent mmap call
  482. *
  483. * This is a fixed-size type for 32/64 compatibility.
  484. */
  485. __u64 offset;
  486. };
  487. struct drm_i915_gem_set_domain {
  488. /** Handle for the object */
  489. __u32 handle;
  490. /** New read domains */
  491. __u32 read_domains;
  492. /** New write domain */
  493. __u32 write_domain;
  494. };
  495. struct drm_i915_gem_sw_finish {
  496. /** Handle for the object */
  497. __u32 handle;
  498. };
  499. struct drm_i915_gem_relocation_entry {
  500. /**
  501. * Handle of the buffer being pointed to by this relocation entry.
  502. *
  503. * It's appealing to make this be an index into the mm_validate_entry
  504. * list to refer to the buffer, but this allows the driver to create
  505. * a relocation list for state buffers and not re-write it per
  506. * exec using the buffer.
  507. */
  508. __u32 target_handle;
  509. /**
  510. * Value to be added to the offset of the target buffer to make up
  511. * the relocation entry.
  512. */
  513. __u32 delta;
  514. /** Offset in the buffer the relocation entry will be written into */
  515. __u64 offset;
  516. /**
  517. * Offset value of the target buffer that the relocation entry was last
  518. * written as.
  519. *
  520. * If the buffer has the same offset as last time, we can skip syncing
  521. * and writing the relocation. This value is written back out by
  522. * the execbuffer ioctl when the relocation is written.
  523. */
  524. __u64 presumed_offset;
  525. /**
  526. * Target memory domains read by this operation.
  527. */
  528. __u32 read_domains;
  529. /**
  530. * Target memory domains written by this operation.
  531. *
  532. * Note that only one domain may be written by the whole
  533. * execbuffer operation, so that where there are conflicts,
  534. * the application will get -EINVAL back.
  535. */
  536. __u32 write_domain;
  537. };
  538. /** @{
  539. * Intel memory domains
  540. *
  541. * Most of these just align with the various caches in
  542. * the system and are used to flush and invalidate as
  543. * objects end up cached in different domains.
  544. */
  545. /** CPU cache */
  546. #define I915_GEM_DOMAIN_CPU 0x00000001
  547. /** Render cache, used by 2D and 3D drawing */
  548. #define I915_GEM_DOMAIN_RENDER 0x00000002
  549. /** Sampler cache, used by texture engine */
  550. #define I915_GEM_DOMAIN_SAMPLER 0x00000004
  551. /** Command queue, used to load batch buffers */
  552. #define I915_GEM_DOMAIN_COMMAND 0x00000008
  553. /** Instruction cache, used by shader programs */
  554. #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
  555. /** Vertex address cache */
  556. #define I915_GEM_DOMAIN_VERTEX 0x00000020
  557. /** GTT domain - aperture and scanout */
  558. #define I915_GEM_DOMAIN_GTT 0x00000040
  559. /** @} */
  560. struct drm_i915_gem_exec_object {
  561. /**
  562. * User's handle for a buffer to be bound into the GTT for this
  563. * operation.
  564. */
  565. __u32 handle;
  566. /** Number of relocations to be performed on this buffer */
  567. __u32 relocation_count;
  568. /**
  569. * Pointer to array of struct drm_i915_gem_relocation_entry containing
  570. * the relocations to be performed in this buffer.
  571. */
  572. __u64 relocs_ptr;
  573. /** Required alignment in graphics aperture */
  574. __u64 alignment;
  575. /**
  576. * Returned value of the updated offset of the object, for future
  577. * presumed_offset writes.
  578. */
  579. __u64 offset;
  580. };
  581. struct drm_i915_gem_execbuffer {
  582. /**
  583. * List of buffers to be validated with their relocations to be
  584. * performend on them.
  585. *
  586. * This is a pointer to an array of struct drm_i915_gem_validate_entry.
  587. *
  588. * These buffers must be listed in an order such that all relocations
  589. * a buffer is performing refer to buffers that have already appeared
  590. * in the validate list.
  591. */
  592. __u64 buffers_ptr;
  593. __u32 buffer_count;
  594. /** Offset in the batchbuffer to start execution from. */
  595. __u32 batch_start_offset;
  596. /** Bytes used in batchbuffer from batch_start_offset */
  597. __u32 batch_len;
  598. __u32 DR1;
  599. __u32 DR4;
  600. __u32 num_cliprects;
  601. /** This is a struct drm_clip_rect *cliprects */
  602. __u64 cliprects_ptr;
  603. };
  604. struct drm_i915_gem_exec_object2 {
  605. /**
  606. * User's handle for a buffer to be bound into the GTT for this
  607. * operation.
  608. */
  609. __u32 handle;
  610. /** Number of relocations to be performed on this buffer */
  611. __u32 relocation_count;
  612. /**
  613. * Pointer to array of struct drm_i915_gem_relocation_entry containing
  614. * the relocations to be performed in this buffer.
  615. */
  616. __u64 relocs_ptr;
  617. /** Required alignment in graphics aperture */
  618. __u64 alignment;
  619. /**
  620. * Returned value of the updated offset of the object, for future
  621. * presumed_offset writes.
  622. */
  623. __u64 offset;
  624. #define EXEC_OBJECT_NEEDS_FENCE (1<<0)
  625. #define EXEC_OBJECT_NEEDS_GTT (1<<1)
  626. #define EXEC_OBJECT_WRITE (1<<2)
  627. #define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
  628. #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_SUPPORTS_48B_ADDRESS<<1)
  629. __u64 flags;
  630. __u64 rsvd1;
  631. __u64 rsvd2;
  632. };
  633. struct drm_i915_gem_execbuffer2 {
  634. /**
  635. * List of gem_exec_object2 structs
  636. */
  637. __u64 buffers_ptr;
  638. __u32 buffer_count;
  639. /** Offset in the batchbuffer to start execution from. */
  640. __u32 batch_start_offset;
  641. /** Bytes used in batchbuffer from batch_start_offset */
  642. __u32 batch_len;
  643. __u32 DR1;
  644. __u32 DR4;
  645. __u32 num_cliprects;
  646. /** This is a struct drm_clip_rect *cliprects */
  647. __u64 cliprects_ptr;
  648. #define I915_EXEC_RING_MASK (7<<0)
  649. #define I915_EXEC_DEFAULT (0<<0)
  650. #define I915_EXEC_RENDER (1<<0)
  651. #define I915_EXEC_BSD (2<<0)
  652. #define I915_EXEC_BLT (3<<0)
  653. #define I915_EXEC_VEBOX (4<<0)
  654. /* Used for switching the constants addressing mode on gen4+ RENDER ring.
  655. * Gen6+ only supports relative addressing to dynamic state (default) and
  656. * absolute addressing.
  657. *
  658. * These flags are ignored for the BSD and BLT rings.
  659. */
  660. #define I915_EXEC_CONSTANTS_MASK (3<<6)
  661. #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
  662. #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
  663. #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
  664. __u64 flags;
  665. __u64 rsvd1; /* now used for context info */
  666. __u64 rsvd2;
  667. };
  668. /** Resets the SO write offset registers for transform feedback on gen7. */
  669. #define I915_EXEC_GEN7_SOL_RESET (1<<8)
  670. /** Request a privileged ("secure") batch buffer. Note only available for
  671. * DRM_ROOT_ONLY | DRM_MASTER processes.
  672. */
  673. #define I915_EXEC_SECURE (1<<9)
  674. /** Inform the kernel that the batch is and will always be pinned. This
  675. * negates the requirement for a workaround to be performed to avoid
  676. * an incoherent CS (such as can be found on 830/845). If this flag is
  677. * not passed, the kernel will endeavour to make sure the batch is
  678. * coherent with the CS before execution. If this flag is passed,
  679. * userspace assumes the responsibility for ensuring the same.
  680. */
  681. #define I915_EXEC_IS_PINNED (1<<10)
  682. /** Provide a hint to the kernel that the command stream and auxiliary
  683. * state buffers already holds the correct presumed addresses and so the
  684. * relocation process may be skipped if no buffers need to be moved in
  685. * preparation for the execbuffer.
  686. */
  687. #define I915_EXEC_NO_RELOC (1<<11)
  688. /** Use the reloc.handle as an index into the exec object array rather
  689. * than as the per-file handle.
  690. */
  691. #define I915_EXEC_HANDLE_LUT (1<<12)
  692. /** Used for switching BSD rings on the platforms with two BSD rings */
  693. #define I915_EXEC_BSD_MASK (3<<13)
  694. #define I915_EXEC_BSD_DEFAULT (0<<13) /* default ping-pong mode */
  695. #define I915_EXEC_BSD_RING1 (1<<13)
  696. #define I915_EXEC_BSD_RING2 (2<<13)
  697. /** Tell the kernel that the batchbuffer is processed by
  698. * the resource streamer.
  699. */
  700. #define I915_EXEC_RESOURCE_STREAMER (1<<15)
  701. #define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_RESOURCE_STREAMER<<1)
  702. #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
  703. #define i915_execbuffer2_set_context_id(eb2, context) \
  704. (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
  705. #define i915_execbuffer2_get_context_id(eb2) \
  706. ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
  707. struct drm_i915_gem_pin {
  708. /** Handle of the buffer to be pinned. */
  709. __u32 handle;
  710. __u32 pad;
  711. /** alignment required within the aperture */
  712. __u64 alignment;
  713. /** Returned GTT offset of the buffer. */
  714. __u64 offset;
  715. };
  716. struct drm_i915_gem_unpin {
  717. /** Handle of the buffer to be unpinned. */
  718. __u32 handle;
  719. __u32 pad;
  720. };
  721. struct drm_i915_gem_busy {
  722. /** Handle of the buffer to check for busy */
  723. __u32 handle;
  724. /** Return busy status (1 if busy, 0 if idle).
  725. * The high word is used to indicate on which rings the object
  726. * currently resides:
  727. * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc)
  728. */
  729. __u32 busy;
  730. };
  731. /**
  732. * I915_CACHING_NONE
  733. *
  734. * GPU access is not coherent with cpu caches. Default for machines without an
  735. * LLC.
  736. */
  737. #define I915_CACHING_NONE 0
  738. /**
  739. * I915_CACHING_CACHED
  740. *
  741. * GPU access is coherent with cpu caches and furthermore the data is cached in
  742. * last-level caches shared between cpu cores and the gpu GT. Default on
  743. * machines with HAS_LLC.
  744. */
  745. #define I915_CACHING_CACHED 1
  746. /**
  747. * I915_CACHING_DISPLAY
  748. *
  749. * Special GPU caching mode which is coherent with the scanout engines.
  750. * Transparently falls back to I915_CACHING_NONE on platforms where no special
  751. * cache mode (like write-through or gfdt flushing) is available. The kernel
  752. * automatically sets this mode when using a buffer as a scanout target.
  753. * Userspace can manually set this mode to avoid a costly stall and clflush in
  754. * the hotpath of drawing the first frame.
  755. */
  756. #define I915_CACHING_DISPLAY 2
  757. struct drm_i915_gem_caching {
  758. /**
  759. * Handle of the buffer to set/get the caching level of. */
  760. __u32 handle;
  761. /**
  762. * Cacheing level to apply or return value
  763. *
  764. * bits0-15 are for generic caching control (i.e. the above defined
  765. * values). bits16-31 are reserved for platform-specific variations
  766. * (e.g. l3$ caching on gen7). */
  767. __u32 caching;
  768. };
  769. #define I915_TILING_NONE 0
  770. #define I915_TILING_X 1
  771. #define I915_TILING_Y 2
  772. #define I915_BIT_6_SWIZZLE_NONE 0
  773. #define I915_BIT_6_SWIZZLE_9 1
  774. #define I915_BIT_6_SWIZZLE_9_10 2
  775. #define I915_BIT_6_SWIZZLE_9_11 3
  776. #define I915_BIT_6_SWIZZLE_9_10_11 4
  777. /* Not seen by userland */
  778. #define I915_BIT_6_SWIZZLE_UNKNOWN 5
  779. /* Seen by userland. */
  780. #define I915_BIT_6_SWIZZLE_9_17 6
  781. #define I915_BIT_6_SWIZZLE_9_10_17 7
  782. struct drm_i915_gem_set_tiling {
  783. /** Handle of the buffer to have its tiling state updated */
  784. __u32 handle;
  785. /**
  786. * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
  787. * I915_TILING_Y).
  788. *
  789. * This value is to be set on request, and will be updated by the
  790. * kernel on successful return with the actual chosen tiling layout.
  791. *
  792. * The tiling mode may be demoted to I915_TILING_NONE when the system
  793. * has bit 6 swizzling that can't be managed correctly by GEM.
  794. *
  795. * Buffer contents become undefined when changing tiling_mode.
  796. */
  797. __u32 tiling_mode;
  798. /**
  799. * Stride in bytes for the object when in I915_TILING_X or
  800. * I915_TILING_Y.
  801. */
  802. __u32 stride;
  803. /**
  804. * Returned address bit 6 swizzling required for CPU access through
  805. * mmap mapping.
  806. */
  807. __u32 swizzle_mode;
  808. };
  809. struct drm_i915_gem_get_tiling {
  810. /** Handle of the buffer to get tiling state for. */
  811. __u32 handle;
  812. /**
  813. * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
  814. * I915_TILING_Y).
  815. */
  816. __u32 tiling_mode;
  817. /**
  818. * Returned address bit 6 swizzling required for CPU access through
  819. * mmap mapping.
  820. */
  821. __u32 swizzle_mode;
  822. /**
  823. * Returned address bit 6 swizzling required for CPU access through
  824. * mmap mapping whilst bound.
  825. */
  826. __u32 phys_swizzle_mode;
  827. };
  828. struct drm_i915_gem_get_aperture {
  829. /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
  830. __u64 aper_size;
  831. /**
  832. * Available space in the aperture used by i915_gem_execbuffer, in
  833. * bytes
  834. */
  835. __u64 aper_available_size;
  836. };
  837. struct drm_i915_get_pipe_from_crtc_id {
  838. /** ID of CRTC being requested **/
  839. __u32 crtc_id;
  840. /** pipe of requested CRTC **/
  841. __u32 pipe;
  842. };
  843. #define I915_MADV_WILLNEED 0
  844. #define I915_MADV_DONTNEED 1
  845. #define __I915_MADV_PURGED 2 /* internal state */
  846. struct drm_i915_gem_madvise {
  847. /** Handle of the buffer to change the backing store advice */
  848. __u32 handle;
  849. /* Advice: either the buffer will be needed again in the near future,
  850. * or wont be and could be discarded under memory pressure.
  851. */
  852. __u32 madv;
  853. /** Whether the backing store still exists. */
  854. __u32 retained;
  855. };
  856. /* flags */
  857. #define I915_OVERLAY_TYPE_MASK 0xff
  858. #define I915_OVERLAY_YUV_PLANAR 0x01
  859. #define I915_OVERLAY_YUV_PACKED 0x02
  860. #define I915_OVERLAY_RGB 0x03
  861. #define I915_OVERLAY_DEPTH_MASK 0xff00
  862. #define I915_OVERLAY_RGB24 0x1000
  863. #define I915_OVERLAY_RGB16 0x2000
  864. #define I915_OVERLAY_RGB15 0x3000
  865. #define I915_OVERLAY_YUV422 0x0100
  866. #define I915_OVERLAY_YUV411 0x0200
  867. #define I915_OVERLAY_YUV420 0x0300
  868. #define I915_OVERLAY_YUV410 0x0400
  869. #define I915_OVERLAY_SWAP_MASK 0xff0000
  870. #define I915_OVERLAY_NO_SWAP 0x000000
  871. #define I915_OVERLAY_UV_SWAP 0x010000
  872. #define I915_OVERLAY_Y_SWAP 0x020000
  873. #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
  874. #define I915_OVERLAY_FLAGS_MASK 0xff000000
  875. #define I915_OVERLAY_ENABLE 0x01000000
  876. struct drm_intel_overlay_put_image {
  877. /* various flags and src format description */
  878. __u32 flags;
  879. /* source picture description */
  880. __u32 bo_handle;
  881. /* stride values and offsets are in bytes, buffer relative */
  882. __u16 stride_Y; /* stride for packed formats */
  883. __u16 stride_UV;
  884. __u32 offset_Y; /* offset for packet formats */
  885. __u32 offset_U;
  886. __u32 offset_V;
  887. /* in pixels */
  888. __u16 src_width;
  889. __u16 src_height;
  890. /* to compensate the scaling factors for partially covered surfaces */
  891. __u16 src_scan_width;
  892. __u16 src_scan_height;
  893. /* output crtc description */
  894. __u32 crtc_id;
  895. __u16 dst_x;
  896. __u16 dst_y;
  897. __u16 dst_width;
  898. __u16 dst_height;
  899. };
  900. /* flags */
  901. #define I915_OVERLAY_UPDATE_ATTRS (1<<0)
  902. #define I915_OVERLAY_UPDATE_GAMMA (1<<1)
  903. #define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2)
  904. struct drm_intel_overlay_attrs {
  905. __u32 flags;
  906. __u32 color_key;
  907. __s32 brightness;
  908. __u32 contrast;
  909. __u32 saturation;
  910. __u32 gamma0;
  911. __u32 gamma1;
  912. __u32 gamma2;
  913. __u32 gamma3;
  914. __u32 gamma4;
  915. __u32 gamma5;
  916. };
  917. /*
  918. * Intel sprite handling
  919. *
  920. * Color keying works with a min/mask/max tuple. Both source and destination
  921. * color keying is allowed.
  922. *
  923. * Source keying:
  924. * Sprite pixels within the min & max values, masked against the color channels
  925. * specified in the mask field, will be transparent. All other pixels will
  926. * be displayed on top of the primary plane. For RGB surfaces, only the min
  927. * and mask fields will be used; ranged compares are not allowed.
  928. *
  929. * Destination keying:
  930. * Primary plane pixels that match the min value, masked against the color
  931. * channels specified in the mask field, will be replaced by corresponding
  932. * pixels from the sprite plane.
  933. *
  934. * Note that source & destination keying are exclusive; only one can be
  935. * active on a given plane.
  936. */
  937. #define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */
  938. #define I915_SET_COLORKEY_DESTINATION (1<<1)
  939. #define I915_SET_COLORKEY_SOURCE (1<<2)
  940. struct drm_intel_sprite_colorkey {
  941. __u32 plane_id;
  942. __u32 min_value;
  943. __u32 channel_mask;
  944. __u32 max_value;
  945. __u32 flags;
  946. };
  947. struct drm_i915_gem_wait {
  948. /** Handle of BO we shall wait on */
  949. __u32 bo_handle;
  950. __u32 flags;
  951. /** Number of nanoseconds to wait, Returns time remaining. */
  952. __s64 timeout_ns;
  953. };
  954. struct drm_i915_gem_context_create {
  955. /* output: id of new context*/
  956. __u32 ctx_id;
  957. __u32 pad;
  958. };
  959. struct drm_i915_gem_context_destroy {
  960. __u32 ctx_id;
  961. __u32 pad;
  962. };
  963. struct drm_i915_reg_read {
  964. __u64 offset;
  965. __u64 val; /* Return value */
  966. };
  967. /* Known registers:
  968. *
  969. * Render engine timestamp - 0x2358 + 64bit - gen7+
  970. * - Note this register returns an invalid value if using the default
  971. * single instruction 8byte read, in order to workaround that use
  972. * offset (0x2538 | 1) instead.
  973. *
  974. */
  975. struct drm_i915_reset_stats {
  976. __u32 ctx_id;
  977. __u32 flags;
  978. /* All resets since boot/module reload, for all contexts */
  979. __u32 reset_count;
  980. /* Number of batches lost when active in GPU, for this context */
  981. __u32 batch_active;
  982. /* Number of batches lost pending for execution, for this context */
  983. __u32 batch_pending;
  984. __u32 pad;
  985. };
  986. struct drm_i915_gem_userptr {
  987. __u64 user_ptr;
  988. __u64 user_size;
  989. __u32 flags;
  990. #define I915_USERPTR_READ_ONLY 0x1
  991. #define I915_USERPTR_UNSYNCHRONIZED 0x80000000
  992. /**
  993. * Returned handle for the object.
  994. *
  995. * Object handles are nonzero.
  996. */
  997. __u32 handle;
  998. };
  999. struct drm_i915_gem_context_param {
  1000. __u32 ctx_id;
  1001. __u32 size;
  1002. __u64 param;
  1003. #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
  1004. #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
  1005. __u64 value;
  1006. };
  1007. #endif /* _I915_DRM_H_ */