msm_drm.h 8.1 KB

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  1. /*
  2. * Copyright (C) 2013 Red Hat
  3. * Author: Rob Clark <robdclark@gmail.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published by
  7. * the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program. If not, see <http://www.gnu.org/licenses/>.
  16. */
  17. #ifndef __MSM_DRM_H__
  18. #define __MSM_DRM_H__
  19. #include <stddef.h>
  20. #include <drm/drm.h>
  21. /* Please note that modifications to all structs defined here are
  22. * subject to backwards-compatibility constraints:
  23. * 1) Do not use pointers, use __u64 instead for 32 bit / 64 bit
  24. * user/kernel compatibility
  25. * 2) Keep fields aligned to their size
  26. * 3) Because of how drm_ioctl() works, we can add new fields at
  27. * the end of an ioctl if some care is taken: drm_ioctl() will
  28. * zero out the new fields at the tail of the ioctl, so a zero
  29. * value should have a backwards compatible meaning. And for
  30. * output params, userspace won't see the newly added output
  31. * fields.. so that has to be somehow ok.
  32. */
  33. #define MSM_PIPE_NONE 0x00
  34. #define MSM_PIPE_2D0 0x01
  35. #define MSM_PIPE_2D1 0x02
  36. #define MSM_PIPE_3D0 0x10
  37. /* timeouts are specified in clock-monotonic absolute times (to simplify
  38. * restarting interrupted ioctls). The following struct is logically the
  39. * same as 'struct timespec' but 32/64b ABI safe.
  40. */
  41. struct drm_msm_timespec {
  42. __s64 tv_sec; /* seconds */
  43. __s64 tv_nsec; /* nanoseconds */
  44. };
  45. #define MSM_PARAM_GPU_ID 0x01
  46. #define MSM_PARAM_GMEM_SIZE 0x02
  47. #define MSM_PARAM_CHIP_ID 0x03
  48. struct drm_msm_param {
  49. __u32 pipe; /* in, MSM_PIPE_x */
  50. __u32 param; /* in, MSM_PARAM_x */
  51. __u64 value; /* out (get_param) or in (set_param) */
  52. };
  53. /*
  54. * GEM buffers:
  55. */
  56. #define MSM_BO_SCANOUT 0x00000001 /* scanout capable */
  57. #define MSM_BO_GPU_READONLY 0x00000002
  58. #define MSM_BO_CACHE_MASK 0x000f0000
  59. /* cache modes */
  60. #define MSM_BO_CACHED 0x00010000
  61. #define MSM_BO_WC 0x00020000
  62. #define MSM_BO_UNCACHED 0x00040000
  63. #define MSM_BO_FLAGS (MSM_BO_SCANOUT | \
  64. MSM_BO_GPU_READONLY | \
  65. MSM_BO_CACHED | \
  66. MSM_BO_WC | \
  67. MSM_BO_UNCACHED)
  68. struct drm_msm_gem_new {
  69. __u64 size; /* in */
  70. __u32 flags; /* in, mask of MSM_BO_x */
  71. __u32 handle; /* out */
  72. };
  73. struct drm_msm_gem_info {
  74. __u32 handle; /* in */
  75. __u32 pad;
  76. __u64 offset; /* out, offset to pass to mmap() */
  77. };
  78. #define MSM_PREP_READ 0x01
  79. #define MSM_PREP_WRITE 0x02
  80. #define MSM_PREP_NOSYNC 0x04
  81. #define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC)
  82. struct drm_msm_gem_cpu_prep {
  83. __u32 handle; /* in */
  84. __u32 op; /* in, mask of MSM_PREP_x */
  85. struct drm_msm_timespec timeout; /* in */
  86. };
  87. struct drm_msm_gem_cpu_fini {
  88. __u32 handle; /* in */
  89. };
  90. /*
  91. * Cmdstream Submission:
  92. */
  93. /* The value written into the cmdstream is logically:
  94. *
  95. * ((relocbuf->gpuaddr + reloc_offset) << shift) | or
  96. *
  97. * When we have GPU's w/ >32bit ptrs, it should be possible to deal
  98. * with this by emit'ing two reloc entries with appropriate shift
  99. * values. Or a new MSM_SUBMIT_CMD_x type would also be an option.
  100. *
  101. * NOTE that reloc's must be sorted by order of increasing submit_offset,
  102. * otherwise EINVAL.
  103. */
  104. struct drm_msm_gem_submit_reloc {
  105. __u32 submit_offset; /* in, offset from submit_bo */
  106. __u32 or; /* in, value OR'd with result */
  107. __s32 shift; /* in, amount of left shift (can be negative) */
  108. __u32 reloc_idx; /* in, index of reloc_bo buffer */
  109. __u64 reloc_offset; /* in, offset from start of reloc_bo */
  110. };
  111. /* submit-types:
  112. * BUF - this cmd buffer is executed normally.
  113. * IB_TARGET_BUF - this cmd buffer is an IB target. Reloc's are
  114. * processed normally, but the kernel does not setup an IB to
  115. * this buffer in the first-level ringbuffer
  116. * CTX_RESTORE_BUF - only executed if there has been a GPU context
  117. * switch since the last SUBMIT ioctl
  118. */
  119. #define MSM_SUBMIT_CMD_BUF 0x0001
  120. #define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002
  121. #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003
  122. struct drm_msm_gem_submit_cmd {
  123. __u32 type; /* in, one of MSM_SUBMIT_CMD_x */
  124. __u32 submit_idx; /* in, index of submit_bo cmdstream buffer */
  125. __u32 submit_offset; /* in, offset into submit_bo */
  126. __u32 size; /* in, cmdstream size */
  127. __u32 pad;
  128. __u32 nr_relocs; /* in, number of submit_reloc's */
  129. __u64 relocs; /* in, ptr to array of submit_reloc's */
  130. };
  131. /* Each buffer referenced elsewhere in the cmdstream submit (ie. the
  132. * cmdstream buffer(s) themselves or reloc entries) has one (and only
  133. * one) entry in the submit->bos[] table.
  134. *
  135. * As a optimization, the current buffer (gpu virtual address) can be
  136. * passed back through the 'presumed' field. If on a subsequent reloc,
  137. * userspace passes back a 'presumed' address that is still valid,
  138. * then patching the cmdstream for this entry is skipped. This can
  139. * avoid kernel needing to map/access the cmdstream bo in the common
  140. * case.
  141. */
  142. #define MSM_SUBMIT_BO_READ 0x0001
  143. #define MSM_SUBMIT_BO_WRITE 0x0002
  144. #define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE)
  145. struct drm_msm_gem_submit_bo {
  146. __u32 flags; /* in, mask of MSM_SUBMIT_BO_x */
  147. __u32 handle; /* in, GEM handle */
  148. __u64 presumed; /* in/out, presumed buffer address */
  149. };
  150. /* Each cmdstream submit consists of a table of buffers involved, and
  151. * one or more cmdstream buffers. This allows for conditional execution
  152. * (context-restore), and IB buffers needed for per tile/bin draw cmds.
  153. */
  154. struct drm_msm_gem_submit {
  155. __u32 pipe; /* in, MSM_PIPE_x */
  156. __u32 fence; /* out */
  157. __u32 nr_bos; /* in, number of submit_bo's */
  158. __u32 nr_cmds; /* in, number of submit_cmd's */
  159. __u64 bos; /* in, ptr to array of submit_bo's */
  160. __u64 cmds; /* in, ptr to array of submit_cmd's */
  161. };
  162. /* The normal way to synchronize with the GPU is just to CPU_PREP on
  163. * a buffer if you need to access it from the CPU (other cmdstream
  164. * submission from same or other contexts, PAGE_FLIP ioctl, etc, all
  165. * handle the required synchronization under the hood). This ioctl
  166. * mainly just exists as a way to implement the gallium pipe_fence
  167. * APIs without requiring a dummy bo to synchronize on.
  168. */
  169. struct drm_msm_wait_fence {
  170. __u32 fence; /* in */
  171. __u32 pad;
  172. struct drm_msm_timespec timeout; /* in */
  173. };
  174. #define DRM_MSM_GET_PARAM 0x00
  175. /* placeholder:
  176. #define DRM_MSM_SET_PARAM 0x01
  177. */
  178. #define DRM_MSM_GEM_NEW 0x02
  179. #define DRM_MSM_GEM_INFO 0x03
  180. #define DRM_MSM_GEM_CPU_PREP 0x04
  181. #define DRM_MSM_GEM_CPU_FINI 0x05
  182. #define DRM_MSM_GEM_SUBMIT 0x06
  183. #define DRM_MSM_WAIT_FENCE 0x07
  184. #define DRM_MSM_NUM_IOCTLS 0x08
  185. #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
  186. #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
  187. #define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
  188. #define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
  189. #define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
  190. #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
  191. #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
  192. #endif /* __MSM_DRM_H__ */