cyclades.h 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493
  1. /* $Revision: 3.0 $$Date: 1998/11/02 14:20:59 $
  2. * linux/include/linux/cyclades.h
  3. *
  4. * This file was initially written by
  5. * Randolph Bentson <bentson@grieg.seaslug.org> and is maintained by
  6. * Ivan Passos <ivan@cyclades.com>.
  7. *
  8. * This file contains the general definitions for the cyclades.c driver
  9. *$Log: cyclades.h,v $
  10. *Revision 3.1 2002/01/29 11:36:16 henrique
  11. *added throttle field on struct cyclades_port to indicate whether the
  12. *port is throttled or not
  13. *
  14. *Revision 3.1 2000/04/19 18:52:52 ivan
  15. *converted address fields to unsigned long and added fields for physical
  16. *addresses on cyclades_card structure;
  17. *
  18. *Revision 3.0 1998/11/02 14:20:59 ivan
  19. *added nports field on cyclades_card structure;
  20. *
  21. *Revision 2.5 1998/08/03 16:57:01 ivan
  22. *added cyclades_idle_stats structure;
  23. *
  24. *Revision 2.4 1998/06/01 12:09:53 ivan
  25. *removed closing_wait2 from cyclades_port structure;
  26. *
  27. *Revision 2.3 1998/03/16 18:01:12 ivan
  28. *changes in the cyclades_port structure to get it closer to the
  29. *standard serial port structure;
  30. *added constants for new ioctls;
  31. *
  32. *Revision 2.2 1998/02/17 16:50:00 ivan
  33. *changes in the cyclades_port structure (addition of shutdown_wait and
  34. *chip_rev variables);
  35. *added constants for new ioctls and for CD1400 rev. numbers.
  36. *
  37. *Revision 2.1 1997/10/24 16:03:00 ivan
  38. *added rflow (which allows enabling the CD1400 special flow control
  39. *feature) and rtsdtr_inv (which allows DTR/RTS pin inversion) to
  40. *cyclades_port structure;
  41. *added Alpha support
  42. *
  43. *Revision 2.0 1997/06/30 10:30:00 ivan
  44. *added some new doorbell command constants related to IOCTLW and
  45. *UART error signaling
  46. *
  47. *Revision 1.8 1997/06/03 15:30:00 ivan
  48. *added constant ZFIRM_HLT
  49. *added constant CyPCI_Ze_win ( = 2 * Cy_PCI_Zwin)
  50. *
  51. *Revision 1.7 1997/03/26 10:30:00 daniel
  52. *new entries at the end of cyclades_port struct to reallocate
  53. *variables illegally allocated within card memory.
  54. *
  55. *Revision 1.6 1996/09/09 18:35:30 bentson
  56. *fold in changes for Cyclom-Z -- including structures for
  57. *communicating with board as well modest changes to original
  58. *structures to support new features.
  59. *
  60. *Revision 1.5 1995/11/13 21:13:31 bentson
  61. *changes suggested by Michael Chastain <mec@duracef.shout.net>
  62. *to support use of this file in non-kernel applications
  63. *
  64. *
  65. */
  66. #ifndef _LINUX_CYCLADES_H
  67. #define _LINUX_CYCLADES_H
  68. #include <linux/types.h>
  69. struct cyclades_monitor {
  70. unsigned long int_count;
  71. unsigned long char_count;
  72. unsigned long char_max;
  73. unsigned long char_last;
  74. };
  75. /*
  76. * These stats all reflect activity since the device was last initialized.
  77. * (i.e., since the port was opened with no other processes already having it
  78. * open)
  79. */
  80. struct cyclades_idle_stats {
  81. __kernel_time_t in_use; /* Time device has been in use (secs) */
  82. __kernel_time_t recv_idle; /* Time since last char received (secs) */
  83. __kernel_time_t xmit_idle; /* Time since last char transmitted (secs) */
  84. unsigned long recv_bytes; /* Bytes received */
  85. unsigned long xmit_bytes; /* Bytes transmitted */
  86. unsigned long overruns; /* Input overruns */
  87. unsigned long frame_errs; /* Input framing errors */
  88. unsigned long parity_errs; /* Input parity errors */
  89. };
  90. #define CYCLADES_MAGIC 0x4359
  91. #define CYGETMON 0x435901
  92. #define CYGETTHRESH 0x435902
  93. #define CYSETTHRESH 0x435903
  94. #define CYGETDEFTHRESH 0x435904
  95. #define CYSETDEFTHRESH 0x435905
  96. #define CYGETTIMEOUT 0x435906
  97. #define CYSETTIMEOUT 0x435907
  98. #define CYGETDEFTIMEOUT 0x435908
  99. #define CYSETDEFTIMEOUT 0x435909
  100. #define CYSETRFLOW 0x43590a
  101. #define CYGETRFLOW 0x43590b
  102. #define CYSETRTSDTR_INV 0x43590c
  103. #define CYGETRTSDTR_INV 0x43590d
  104. #define CYZSETPOLLCYCLE 0x43590e
  105. #define CYZGETPOLLCYCLE 0x43590f
  106. #define CYGETCD1400VER 0x435910
  107. #define CYSETWAIT 0x435912
  108. #define CYGETWAIT 0x435913
  109. /*************** CYCLOM-Z ADDITIONS ***************/
  110. #define CZIOC ('M' << 8)
  111. #define CZ_NBOARDS (CZIOC|0xfa)
  112. #define CZ_BOOT_START (CZIOC|0xfb)
  113. #define CZ_BOOT_DATA (CZIOC|0xfc)
  114. #define CZ_BOOT_END (CZIOC|0xfd)
  115. #define CZ_TEST (CZIOC|0xfe)
  116. #define CZ_DEF_POLL (HZ/25)
  117. #define MAX_BOARD 4 /* Max number of boards */
  118. #define MAX_DEV 256 /* Max number of ports total */
  119. #define CYZ_MAX_SPEED 921600
  120. #define CYZ_FIFO_SIZE 16
  121. #define CYZ_BOOT_NWORDS 0x100
  122. struct CYZ_BOOT_CTRL {
  123. unsigned short nboard;
  124. int status[MAX_BOARD];
  125. int nchannel[MAX_BOARD];
  126. int fw_rev[MAX_BOARD];
  127. unsigned long offset;
  128. unsigned long data[CYZ_BOOT_NWORDS];
  129. };
  130. #ifndef DP_WINDOW_SIZE
  131. /*
  132. * Memory Window Sizes
  133. */
  134. #define DP_WINDOW_SIZE (0x00080000) /* window size 512 Kb */
  135. #define ZE_DP_WINDOW_SIZE (0x00100000) /* window size 1 Mb (Ze and
  136. 8Zo V.2 */
  137. #define CTRL_WINDOW_SIZE (0x00000080) /* runtime regs 128 bytes */
  138. /*
  139. * CUSTOM_REG - Cyclom-Z/PCI Custom Registers Set. The driver
  140. * normally will access only interested on the fpga_id, fpga_version,
  141. * start_cpu and stop_cpu.
  142. */
  143. struct CUSTOM_REG {
  144. __u32 fpga_id; /* FPGA Identification Register */
  145. __u32 fpga_version; /* FPGA Version Number Register */
  146. __u32 cpu_start; /* CPU start Register (write) */
  147. __u32 cpu_stop; /* CPU stop Register (write) */
  148. __u32 misc_reg; /* Miscellaneous Register */
  149. __u32 idt_mode; /* IDT mode Register */
  150. __u32 uart_irq_status; /* UART IRQ status Register */
  151. __u32 clear_timer0_irq; /* Clear timer interrupt Register */
  152. __u32 clear_timer1_irq; /* Clear timer interrupt Register */
  153. __u32 clear_timer2_irq; /* Clear timer interrupt Register */
  154. __u32 test_register; /* Test Register */
  155. __u32 test_count; /* Test Count Register */
  156. __u32 timer_select; /* Timer select register */
  157. __u32 pr_uart_irq_status; /* Prioritized UART IRQ stat Reg */
  158. __u32 ram_wait_state; /* RAM wait-state Register */
  159. __u32 uart_wait_state; /* UART wait-state Register */
  160. __u32 timer_wait_state; /* timer wait-state Register */
  161. __u32 ack_wait_state; /* ACK wait State Register */
  162. };
  163. /*
  164. * RUNTIME_9060 - PLX PCI9060ES local configuration and shared runtime
  165. * registers. This structure can be used to access the 9060 registers
  166. * (memory mapped).
  167. */
  168. struct RUNTIME_9060 {
  169. __u32 loc_addr_range; /* 00h - Local Address Range */
  170. __u32 loc_addr_base; /* 04h - Local Address Base */
  171. __u32 loc_arbitr; /* 08h - Local Arbitration */
  172. __u32 endian_descr; /* 0Ch - Big/Little Endian Descriptor */
  173. __u32 loc_rom_range; /* 10h - Local ROM Range */
  174. __u32 loc_rom_base; /* 14h - Local ROM Base */
  175. __u32 loc_bus_descr; /* 18h - Local Bus descriptor */
  176. __u32 loc_range_mst; /* 1Ch - Local Range for Master to PCI */
  177. __u32 loc_base_mst; /* 20h - Local Base for Master PCI */
  178. __u32 loc_range_io; /* 24h - Local Range for Master IO */
  179. __u32 pci_base_mst; /* 28h - PCI Base for Master PCI */
  180. __u32 pci_conf_io; /* 2Ch - PCI configuration for Master IO */
  181. __u32 filler1; /* 30h */
  182. __u32 filler2; /* 34h */
  183. __u32 filler3; /* 38h */
  184. __u32 filler4; /* 3Ch */
  185. __u32 mail_box_0; /* 40h - Mail Box 0 */
  186. __u32 mail_box_1; /* 44h - Mail Box 1 */
  187. __u32 mail_box_2; /* 48h - Mail Box 2 */
  188. __u32 mail_box_3; /* 4Ch - Mail Box 3 */
  189. __u32 filler5; /* 50h */
  190. __u32 filler6; /* 54h */
  191. __u32 filler7; /* 58h */
  192. __u32 filler8; /* 5Ch */
  193. __u32 pci_doorbell; /* 60h - PCI to Local Doorbell */
  194. __u32 loc_doorbell; /* 64h - Local to PCI Doorbell */
  195. __u32 intr_ctrl_stat; /* 68h - Interrupt Control/Status */
  196. __u32 init_ctrl; /* 6Ch - EEPROM control, Init Control, etc */
  197. };
  198. /* Values for the Local Base Address re-map register */
  199. #define WIN_RAM 0x00000001L /* set the sliding window to RAM */
  200. #define WIN_CREG 0x14000001L /* set the window to custom Registers */
  201. /* Values timer select registers */
  202. #define TIMER_BY_1M 0x00 /* clock divided by 1M */
  203. #define TIMER_BY_256K 0x01 /* clock divided by 256k */
  204. #define TIMER_BY_128K 0x02 /* clock divided by 128k */
  205. #define TIMER_BY_32K 0x03 /* clock divided by 32k */
  206. /****************** ****************** *******************/
  207. #endif
  208. #ifndef ZFIRM_ID
  209. /* #include "zfwint.h" */
  210. /****************** ****************** *******************/
  211. /*
  212. * This file contains the definitions for interfacing with the
  213. * Cyclom-Z ZFIRM Firmware.
  214. */
  215. /* General Constant definitions */
  216. #define MAX_CHAN 64 /* max number of channels per board */
  217. /* firmware id structure (set after boot) */
  218. #define ID_ADDRESS 0x00000180L /* signature/pointer address */
  219. #define ZFIRM_ID 0x5557465AL /* ZFIRM/U signature */
  220. #define ZFIRM_HLT 0x59505B5CL /* ZFIRM needs external power supply */
  221. #define ZFIRM_RST 0x56040674L /* RST signal (due to FW reset) */
  222. #define ZF_TINACT_DEF 1000 /* default inactivity timeout
  223. (1000 ms) */
  224. #define ZF_TINACT ZF_TINACT_DEF
  225. struct FIRM_ID {
  226. __u32 signature; /* ZFIRM/U signature */
  227. __u32 zfwctrl_addr; /* pointer to ZFW_CTRL structure */
  228. };
  229. /* Op. System id */
  230. #define C_OS_LINUX 0x00000030 /* generic Linux system */
  231. /* channel op_mode */
  232. #define C_CH_DISABLE 0x00000000 /* channel is disabled */
  233. #define C_CH_TXENABLE 0x00000001 /* channel Tx enabled */
  234. #define C_CH_RXENABLE 0x00000002 /* channel Rx enabled */
  235. #define C_CH_ENABLE 0x00000003 /* channel Tx/Rx enabled */
  236. #define C_CH_LOOPBACK 0x00000004 /* Loopback mode */
  237. /* comm_parity - parity */
  238. #define C_PR_NONE 0x00000000 /* None */
  239. #define C_PR_ODD 0x00000001 /* Odd */
  240. #define C_PR_EVEN 0x00000002 /* Even */
  241. #define C_PR_MARK 0x00000004 /* Mark */
  242. #define C_PR_SPACE 0x00000008 /* Space */
  243. #define C_PR_PARITY 0x000000ff
  244. #define C_PR_DISCARD 0x00000100 /* discard char with frame/par error */
  245. #define C_PR_IGNORE 0x00000200 /* ignore frame/par error */
  246. /* comm_data_l - data length and stop bits */
  247. #define C_DL_CS5 0x00000001
  248. #define C_DL_CS6 0x00000002
  249. #define C_DL_CS7 0x00000004
  250. #define C_DL_CS8 0x00000008
  251. #define C_DL_CS 0x0000000f
  252. #define C_DL_1STOP 0x00000010
  253. #define C_DL_15STOP 0x00000020
  254. #define C_DL_2STOP 0x00000040
  255. #define C_DL_STOP 0x000000f0
  256. /* interrupt enabling/status */
  257. #define C_IN_DISABLE 0x00000000 /* zero, disable interrupts */
  258. #define C_IN_TXBEMPTY 0x00000001 /* tx buffer empty */
  259. #define C_IN_TXLOWWM 0x00000002 /* tx buffer below LWM */
  260. #define C_IN_RXHIWM 0x00000010 /* rx buffer above HWM */
  261. #define C_IN_RXNNDT 0x00000020 /* rx no new data timeout */
  262. #define C_IN_MDCD 0x00000100 /* modem DCD change */
  263. #define C_IN_MDSR 0x00000200 /* modem DSR change */
  264. #define C_IN_MRI 0x00000400 /* modem RI change */
  265. #define C_IN_MCTS 0x00000800 /* modem CTS change */
  266. #define C_IN_RXBRK 0x00001000 /* Break received */
  267. #define C_IN_PR_ERROR 0x00002000 /* parity error */
  268. #define C_IN_FR_ERROR 0x00004000 /* frame error */
  269. #define C_IN_OVR_ERROR 0x00008000 /* overrun error */
  270. #define C_IN_RXOFL 0x00010000 /* RX buffer overflow */
  271. #define C_IN_IOCTLW 0x00020000 /* I/O control w/ wait */
  272. #define C_IN_MRTS 0x00040000 /* modem RTS drop */
  273. #define C_IN_ICHAR 0x00080000
  274. /* flow control */
  275. #define C_FL_OXX 0x00000001 /* output Xon/Xoff flow control */
  276. #define C_FL_IXX 0x00000002 /* output Xon/Xoff flow control */
  277. #define C_FL_OIXANY 0x00000004 /* output Xon/Xoff (any xon) */
  278. #define C_FL_SWFLOW 0x0000000f
  279. /* flow status */
  280. #define C_FS_TXIDLE 0x00000000 /* no Tx data in the buffer or UART */
  281. #define C_FS_SENDING 0x00000001 /* UART is sending data */
  282. #define C_FS_SWFLOW 0x00000002 /* Tx is stopped by received Xoff */
  283. /* rs_control/rs_status RS-232 signals */
  284. #define C_RS_PARAM 0x80000000 /* Indicates presence of parameter in
  285. IOCTLM command */
  286. #define C_RS_RTS 0x00000001 /* RTS */
  287. #define C_RS_DTR 0x00000004 /* DTR */
  288. #define C_RS_DCD 0x00000100 /* CD */
  289. #define C_RS_DSR 0x00000200 /* DSR */
  290. #define C_RS_RI 0x00000400 /* RI */
  291. #define C_RS_CTS 0x00000800 /* CTS */
  292. /* commands Host <-> Board */
  293. #define C_CM_RESET 0x01 /* reset/flush buffers */
  294. #define C_CM_IOCTL 0x02 /* re-read CH_CTRL */
  295. #define C_CM_IOCTLW 0x03 /* re-read CH_CTRL, intr when done */
  296. #define C_CM_IOCTLM 0x04 /* RS-232 outputs change */
  297. #define C_CM_SENDXOFF 0x10 /* send Xoff */
  298. #define C_CM_SENDXON 0x11 /* send Xon */
  299. #define C_CM_CLFLOW 0x12 /* Clear flow control (resume) */
  300. #define C_CM_SENDBRK 0x41 /* send break */
  301. #define C_CM_INTBACK 0x42 /* Interrupt back */
  302. #define C_CM_SET_BREAK 0x43 /* Tx break on */
  303. #define C_CM_CLR_BREAK 0x44 /* Tx break off */
  304. #define C_CM_CMD_DONE 0x45 /* Previous command done */
  305. #define C_CM_INTBACK2 0x46 /* Alternate Interrupt back */
  306. #define C_CM_TINACT 0x51 /* set inactivity detection */
  307. #define C_CM_IRQ_ENBL 0x52 /* enable generation of interrupts */
  308. #define C_CM_IRQ_DSBL 0x53 /* disable generation of interrupts */
  309. #define C_CM_ACK_ENBL 0x54 /* enable acknowledged interrupt mode */
  310. #define C_CM_ACK_DSBL 0x55 /* disable acknowledged intr mode */
  311. #define C_CM_FLUSH_RX 0x56 /* flushes Rx buffer */
  312. #define C_CM_FLUSH_TX 0x57 /* flushes Tx buffer */
  313. #define C_CM_Q_ENABLE 0x58 /* enables queue access from the
  314. driver */
  315. #define C_CM_Q_DISABLE 0x59 /* disables queue access from the
  316. driver */
  317. #define C_CM_TXBEMPTY 0x60 /* Tx buffer is empty */
  318. #define C_CM_TXLOWWM 0x61 /* Tx buffer low water mark */
  319. #define C_CM_RXHIWM 0x62 /* Rx buffer high water mark */
  320. #define C_CM_RXNNDT 0x63 /* rx no new data timeout */
  321. #define C_CM_TXFEMPTY 0x64
  322. #define C_CM_ICHAR 0x65
  323. #define C_CM_MDCD 0x70 /* modem DCD change */
  324. #define C_CM_MDSR 0x71 /* modem DSR change */
  325. #define C_CM_MRI 0x72 /* modem RI change */
  326. #define C_CM_MCTS 0x73 /* modem CTS change */
  327. #define C_CM_MRTS 0x74 /* modem RTS drop */
  328. #define C_CM_RXBRK 0x84 /* Break received */
  329. #define C_CM_PR_ERROR 0x85 /* Parity error */
  330. #define C_CM_FR_ERROR 0x86 /* Frame error */
  331. #define C_CM_OVR_ERROR 0x87 /* Overrun error */
  332. #define C_CM_RXOFL 0x88 /* RX buffer overflow */
  333. #define C_CM_CMDERROR 0x90 /* command error */
  334. #define C_CM_FATAL 0x91 /* fatal error */
  335. #define C_CM_HW_RESET 0x92 /* reset board */
  336. /*
  337. * CH_CTRL - This per port structure contains all parameters
  338. * that control an specific port. It can be seen as the
  339. * configuration registers of a "super-serial-controller".
  340. */
  341. struct CH_CTRL {
  342. __u32 op_mode; /* operation mode */
  343. __u32 intr_enable; /* interrupt masking */
  344. __u32 sw_flow; /* SW flow control */
  345. __u32 flow_status; /* output flow status */
  346. __u32 comm_baud; /* baud rate - numerically specified */
  347. __u32 comm_parity; /* parity */
  348. __u32 comm_data_l; /* data length/stop */
  349. __u32 comm_flags; /* other flags */
  350. __u32 hw_flow; /* HW flow control */
  351. __u32 rs_control; /* RS-232 outputs */
  352. __u32 rs_status; /* RS-232 inputs */
  353. __u32 flow_xon; /* xon char */
  354. __u32 flow_xoff; /* xoff char */
  355. __u32 hw_overflow; /* hw overflow counter */
  356. __u32 sw_overflow; /* sw overflow counter */
  357. __u32 comm_error; /* frame/parity error counter */
  358. __u32 ichar;
  359. __u32 filler[7];
  360. };
  361. /*
  362. * BUF_CTRL - This per channel structure contains
  363. * all Tx and Rx buffer control for a given channel.
  364. */
  365. struct BUF_CTRL {
  366. __u32 flag_dma; /* buffers are in Host memory */
  367. __u32 tx_bufaddr; /* address of the tx buffer */
  368. __u32 tx_bufsize; /* tx buffer size */
  369. __u32 tx_threshold; /* tx low water mark */
  370. __u32 tx_get; /* tail index tx buf */
  371. __u32 tx_put; /* head index tx buf */
  372. __u32 rx_bufaddr; /* address of the rx buffer */
  373. __u32 rx_bufsize; /* rx buffer size */
  374. __u32 rx_threshold; /* rx high water mark */
  375. __u32 rx_get; /* tail index rx buf */
  376. __u32 rx_put; /* head index rx buf */
  377. __u32 filler[5]; /* filler to align structures */
  378. };
  379. /*
  380. * BOARD_CTRL - This per board structure contains all global
  381. * control fields related to the board.
  382. */
  383. struct BOARD_CTRL {
  384. /* static info provided by the on-board CPU */
  385. __u32 n_channel; /* number of channels */
  386. __u32 fw_version; /* firmware version */
  387. /* static info provided by the driver */
  388. __u32 op_system; /* op_system id */
  389. __u32 dr_version; /* driver version */
  390. /* board control area */
  391. __u32 inactivity; /* inactivity control */
  392. /* host to FW commands */
  393. __u32 hcmd_channel; /* channel number */
  394. __u32 hcmd_param; /* pointer to parameters */
  395. /* FW to Host commands */
  396. __u32 fwcmd_channel; /* channel number */
  397. __u32 fwcmd_param; /* pointer to parameters */
  398. __u32 zf_int_queue_addr; /* offset for INT_QUEUE structure */
  399. /* filler so the structures are aligned */
  400. __u32 filler[6];
  401. };
  402. /* Host Interrupt Queue */
  403. #define QUEUE_SIZE (10*MAX_CHAN)
  404. struct INT_QUEUE {
  405. unsigned char intr_code[QUEUE_SIZE];
  406. unsigned long channel[QUEUE_SIZE];
  407. unsigned long param[QUEUE_SIZE];
  408. unsigned long put;
  409. unsigned long get;
  410. };
  411. /*
  412. * ZFW_CTRL - This is the data structure that includes all other
  413. * data structures used by the Firmware.
  414. */
  415. struct ZFW_CTRL {
  416. struct BOARD_CTRL board_ctrl;
  417. struct CH_CTRL ch_ctrl[MAX_CHAN];
  418. struct BUF_CTRL buf_ctrl[MAX_CHAN];
  419. };
  420. /****************** ****************** *******************/
  421. #endif
  422. #endif /* _LINUX_CYCLADES_H */